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AgeCommit message (Expand)AuthorFilesLines
2021-04-01Clean up nonexistent/unused properties handlingkn1-12/+1
2021-04-01Hardcode meaningful alert level, track apm's battery state betterkn1-23/+7
2021-03-26Flag sensors as invalid on bogus readskn1-3/+7
2021-03-25Provide apm(4/arm64) with battery informationkn1-1/+41
2021-03-22Load MSI pages through bus_dma(9). Our interrupt controllers for MSIspatrick1-4/+53
2021-03-22Update device-tree bindingskn1-6/+6
2021-03-13Advertise 30-bit color support.kettenis1-2/+5
2021-03-11Make sure to skip attaching disabled I2C devices. This can happen onpatrick5-10/+35
2021-03-11Make sure to skip attaching disabled I2C devices. This can happen onpatrick1-2/+7
2021-03-09Add support for 30-bit color modes.kettenis1-2/+4
2021-03-08Add support for rk809 as seen on the Rock Pi N10 with the rk3399pro. Addkurt1-57/+262
2021-03-01Transactions on the AXI bus contain a Stream ID. SMMUs filterpatrick1-1/+15
2021-03-01The ep-gpios property is optional on the Rockchip PCIe controller.patrick1-11/+21
2021-02-28Issue call to IOMMU OFW API to collect an IOMMU-sprinkled DMA tag.patrick1-1/+7
2021-02-25Add some infrastructure in the PCI chipset tag for pci_probe_device_hook()patrick4-4/+36
2021-02-22Disable double-data rate modes if 1.8V signalling is not possible.patrick1-2/+4
2021-02-22Slow mode is only relevant for legacy and high speed timings.patrick1-3/+3
2021-02-22Improve support for the variant found on the Apple M1 SoC.kettenis2-63/+160
2021-02-16Add support for the UART found on the Apple M1 SoC.kettenis2-10/+30
2021-02-14Introduce variables to deal with bit layout differences in the UFSTATkettenis1-9/+26
2021-02-11Don't hardcode com(4)'s major number in exuart(4).patrick1-5/+12
2021-02-05arm_intr_establish_fdt() has long been renamed to fdt_intr_establish().patrick3-8/+7
2021-02-05Fix CVS tag.patrick1-1/+1
2021-02-05Fix whitespace.patrick1-2/+2
2021-02-05Rename probe/attach functions to fit our regular naming scheme. Replacepatrick1-13/+13
2021-02-05Move exuart(4) to sys/dev/fdt so it can be shared between arm64 and armv7.patrick3-1/+1057
2021-02-04Tedu unnecessary imxuartvar.h.patrick2-21/+1
2021-02-01handle #pinctrl-cells 2jsg1-2/+7
2021-01-20Reprogram outbound windows to match the device tree. Necessary becausekettenis1-3/+34
2021-01-19Implement intx support.kettenis1-18/+122
2020-12-29Handle pinctrl.kettenis1-1/+4
2020-12-29Add more PWM pin descriptions.kettenis1-1/+32
2020-12-28Add support for the PCIe controller found on Amlogic G12A/G12B/SM1 SoCs.kettenis1-11/+119
2020-12-27Remove debug printf.kettenis1-2/+1
2020-12-27Add PCIe support.kettenis1-42/+62
2020-12-27Add PCIe power domain.kettenis1-1/+14
2020-12-22Add PCIe clocks.kettenis1-1/+5
2020-12-22Defer hardware initialization in order to give things like PCIe PHYskettenis1-15/+31
2020-12-19There's no need to include the OFW GPIO header.patrick1-2/+1
2020-12-19Add support for the i.MX8MP PCIe clocks.patrick2-1/+40
2020-12-18Add support for the i.MX8MP second ethernet. The Plus SoC not only has thepatrick2-4/+98
2020-12-18Emulate open drain GPIOs. This replaces the hack added in the last commit.kettenis1-31/+22
2020-12-18Make large read and write transactions work.kettenis1-38/+58
2020-12-18Add glue for the USB3 controller on the i.MX8MP SoC. NXP had this glue forpatrick2-1/+80
2020-12-18Add code to initialize the USB 3 PHY on i.MX8MP.patrick1-2/+65
2020-12-18Add support for the i.MX8MP USB clocks.patrick2-2/+88
2020-12-18Attach imxgpc(4) to i.MX8MP as well.patrick1-1/+3
2020-12-17Only enable the USB 3.0 port and PHY if it is enabled on a board.kettenis1-5/+7
2020-12-17Reset pin 3 of the GPIOAO bank to input mode to work around a hardwarekettenis1-2/+31
2020-12-17Match on "amlogic,meson-g12a-dwmac" which is used by newer Linux mainlinekettenis1-1/+2
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