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2016-08-15For some reason the RTL8211E PHY on the Banana Pi responds to both address 0kettenis2-5/+5
2016-08-14change some types in bio from u_quad_t to uint64_t, and fix casts indlg4-12/+12
2016-08-14replace u_quad_t with uint64_t.dlg1-11/+11
2016-08-13Add the core of the code for dwge(4), a driver for the Synopsis Designwarekettenis3-0/+1806
2016-08-10armish handled some early-gen arm machines, which required tons ofderaadt1-37/+1
2016-07-26Fix byteswap errors in rtwn(4) and urtwn(4) introduced by me on June 17.stsp1-8/+4
2016-07-13remove unused function ether_cmp()deraadt1-13/+1
2016-06-17Merge a lot of code from urtwn(4) into rtwn(4). Both drivers now share codestsp2-165/+323
2016-06-05Continue preparing a future merge of urtwn(4) and rtwn(4).stsp2-293/+342
2016-05-20check we allocated the cq, not the sq, after trying to allocate the cqdlg1-2/+2
2016-05-10make qla_iocb_seg structs 4 byte aligned and use htolem32 to set it.dlg2-6/+10
2016-05-06Make sure we always update both bits that control the bus width. Also makekettenis1-10/+17
2016-05-06Round the requested clock frequency down to a support value instead ofkettenis1-1/+15
2016-05-06Fix the DMA transfer code to repect the block size in the sdmmc command.kettenis1-3/+5
2016-05-05Add Dual Data Rate support for eMMC at 52MHz.kettenis2-6/+6
2016-05-04Use BUS_DMA_OVERRUN to cope with the broken DMA engine of the Davicom DM9102kettenis1-3/+15
2016-05-01Add support for changing the bus width to the sdmmc subsystem and the sdhc(4)kettenis2-9/+4
2016-04-20If RTL8111E on PC Engines APU is detected, configure NIC LEDs to display link.sthen2-2/+27
2016-04-18allocate an array of entries, not pointers for the queuesdlg1-3/+3
2016-04-14shorten the io path slightlydlg1-32/+14
2016-04-14apparently it's spelled NVMe, not NVMEdlg1-2/+2
2016-04-14provide a shutdown hook that follows the procedure in the docsdlg3-6/+109
2016-04-14implement translation of scsi SYNC CACHE to nvme FLUSHdlg1-1/+55
2016-04-14bump openings to 64 to match the number of ccbs.dlg1-2/+2
2016-04-14if io needs more than two prpe slots, overflow into the ccb prpldlg1-2/+25
2016-04-14reallocate the ccbs after we figure out how big the sgls can bedlg1-1/+10
2016-04-14set the scsi status to SCSI_OKdlg1-1/+2
2016-04-14allocate dma memory for ccbs to use as prpe listsdlg1-2/+19
2016-04-14dont attach if the min nvme page size is bigger than the cpu page sizedlg1-4/+8
2016-04-14dont complete scsi writes twicedlg1-2/+2
2016-04-14WAITOK for the dmamap create for ccbs toodlg1-2/+2
2016-04-14cut the memory for io buffers up into page sized chunksdlg1-2/+2
2016-04-14check both the admin and io queue for completions in the interrupt handlerdlg1-2/+8
2016-04-14dont put names in arguments.dlg1-2/+2
2016-04-14tabs, not spacesdlg1-3/+3
2016-04-13implement handling of scsi reads and writesdlg1-1/+126
2016-04-13enable interrupts before attaching the scsibusdlg1-1/+3
2016-04-13allocate a queue for io commands and tell the chip about it.dlg1-1/+14
2016-04-13nvme_q_create() issues the commands to tell the chip about io queuesdlg1-1/+46
2016-04-13stub out handling of TEST_UNIT_READY, PREVENT_ALLOW, and START_STOPdlg1-1/+8
2016-04-13implement handling of scsi read capacity commandsdlg1-2/+78
2016-04-13implement basic scsi inquiry handlingdlg1-1/+59
2016-04-13provide variants of the sqe struct for q creation and io operationsdlg1-1/+61
2016-04-13implement the guts of the scsi probe and free functiondlg1-2/+52
2016-04-13implement the namespace identify structuredlg1-1/+35
2016-04-13the io command setdlg1-1/+8
2016-04-13wire up the scsi midlayer. scsibus should appear after this.dlg2-2/+20
2016-04-13allocate an array of things to hold info about namespacesdlg2-2/+10
2016-04-13stash the controller identify and number of namespaces in the softc.dlg2-4/+13
2016-04-13make a place for q_id to godlg1-1/+2