| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Correct a bit test for DDR2 CAS Latency and recognise CL7 and CL6. |   jsg | 2015-01-25 | 1 | -3/+3 |
| * | Remove dead store causing clang to warn; dhill |   miod | 2015-01-19 | 1 | -2/+1 |
| * | Remove dead assignments and newly created unused variables. |   chl | 2011-04-19 | 1 | -5/+3 |
| * | fix a logic error found by lint | jsg | 2010-06-29 | 1 | -2/+2 |
| * | Split existing spdmem@i2c code into bus-agnostic spd record decoding code, | miod | 2010-03-22 | 1 | -0/+794 |
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index : wireguard-openbsd | |
| WireGuard implementation for the OpenBSD kernel | Matt Dunwoodie |
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