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2020-12-27Remove debug printf.kettenis1-2/+1
2020-12-27Add PCIe support.kettenis1-42/+62
2020-12-27Add PCIe power domain.kettenis1-1/+14
2020-12-27have mcx_process_txeof return the number of slots it processed.dlg1-7/+8
2020-12-27do a bus space barrier after arming the eq.dlg1-2/+2
2020-12-27disable timestamping a little bit harder to avoid divide by 0.dlg1-1/+5
2020-12-27shuffle filling the rx ring so the sw prod is updated before the hw.dlg1-24/+19
2020-12-26reuse the calculated vector as the argument to pci_intr_map_msix.dlg1-2/+2
2020-12-26add bus_dmamap_sync ops around the eq.dlg1-6/+27
2020-12-26add some bus_dmamap_syncs around the rq.dlg1-2/+16
2020-12-26sprinkle some bus_dmamap_syncs around the cq handling.dlg1-1/+14
2020-12-26sprinkle some bus_dmamap_syncs around the sq.dlg1-2/+17
2020-12-26better manage the lifetime of the dmamem used for various rings.dlg1-36/+65
2020-12-26sdmmc(4): sdmmc_io_function_enable(): don't sleep on lboltcheloha1-2/+2
2020-12-25expose the mcx timer as a timecounter.dlg1-1/+30
2020-12-25match on Gemini Lake I2Cjsg1-1/+9
2020-12-25Refactor klist insertion and removalvisa10-34/+34
2020-12-24Do proper accounting of zero length TDs. Currently a specific numbermglocker2-2/+6
2020-12-24Extract clock frequency from _DSD properties.patrick1-1/+3
2020-12-24Implement capability register overrides based on _DSD properties.kettenis1-2/+11
2020-12-24regenjsg2-4/+76
2020-12-24add some NVMe devices and Intel Comet Lake host bridgesjsg1-2/+18
2020-12-24ramdisks do not contain WOLderaadt1-1/+3
2020-12-24Add Wake on LAN support to rge(4).kevlo2-3/+86
2020-12-23Fix regulators that use "active-low" polarity. Our implementation nowkettenis1-9/+16
2020-12-22have the ifrxr info stuff report the buffer size the hw handles.dlg1-2/+2
2020-12-22Add PCIe clocks.kettenis1-1/+5
2020-12-22Defer hardware initialization in order to give things like PCIe PHYskettenis1-15/+31
2020-12-22name the rx rings like ix does for systat mbdlg1-1/+2
2020-12-21Only enable rasops1_putchar8() and rasops1_putchar16() optomizations onkettenis1-5/+5
2020-12-20sync with i915_pciids.hjsg1-2/+0
2020-12-20drm/i915: Remove dubious Valleyview PCI IDsjsg1-3/+1
2020-12-20remove duplicate device id caused by subids in INTEL_IVB_Q_IDSjsg1-1/+0
2020-12-20test against [VM_MIN_ADDRESS, VM_MAXUSER_ADDRESS] in access_ok()jsg1-3/+8
2020-12-19There's no need to include the OFW GPIO header.patrick1-2/+1
2020-12-19Add support for the i.MX8MP PCIe clocks.patrick2-1/+40
2020-12-18Add support for the i.MX8MP second ethernet. The Plus SoC not only has thepatrick2-4/+98
2020-12-18Emulate open drain GPIOs. This replaces the hack added in the last commit.kettenis1-31/+22
2020-12-18Add symbolic constants related to open source and open drain GPIOs.kettenis1-3/+10
2020-12-18Make large read and write transactions work.kettenis1-38/+58
2020-12-18Add glue for the USB3 controller on the i.MX8MP SoC. NXP had this glue forpatrick2-1/+80
2020-12-18Add code to initialize the USB 3 PHY on i.MX8MP.patrick1-2/+65
2020-12-18Add support for the i.MX8MP USB clocks.patrick2-2/+88
2020-12-18Attach imxgpc(4) to i.MX8MP as well.patrick1-1/+3
2020-12-17tht(4): more tsleep(9) -> tsleep_nsec(9)cheloha1-20/+8
2020-12-17Only enable the USB 3.0 port and PHY if it is enabled on a board.kettenis1-5/+7
2020-12-17Reset pin 3 of the GPIOAO bank to input mode to work around a hardwarekettenis1-2/+31
2020-12-17Match on "amlogic,meson-g12a-dwmac" which is used by newer Linux mainlinekettenis1-1/+2
2020-12-17Add support for the "Always On" GPIOs.kettenis1-72/+187
2020-12-17Fix some issues with referencing named ACPI nodes from Packages.kettenis6-58/+65
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