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2020-12-24Extract clock frequency from _DSD properties.patrick1-1/+3
2020-12-24Implement capability register overrides based on _DSD properties.kettenis1-2/+11
2020-12-24regenjsg2-4/+76
2020-12-24add some NVMe devices and Intel Comet Lake host bridgesjsg1-2/+18
2020-12-24Initialize mips64 pmap pool using IPL_VM.visa1-2/+2
2020-12-24ramdisks do not contain WOLderaadt1-1/+3
2020-12-24handle reported core clock frequency of 0 on newer Intel Comet Lakejsg1-1/+3
2020-12-24tsleep(9): add global "nowake" channel for threads avoiding wakeup(9)cheloha2-2/+12
2020-12-24Add Wake on LAN support to rge(4).kevlo2-3/+86
2020-12-23sigsuspend(2): change wmesg from "pause" to "sigsusp"cheloha1-2/+2
2020-12-23nanosleep(2): shorten wmesg from "nanosleep" to "nanoslp"cheloha1-2/+2
2020-12-23Use IPL_VM for the pmap pool like we do on amd64.kettenis1-2/+2
2020-12-23Ensure that filt_dead() takes effectvisa1-1/+2
2020-12-23Clear error before each iteration in kqueue_scan()visa1-1/+3
2020-12-23Fix regulators that use "active-low" polarity. Our implementation nowkettenis1-9/+16
2020-12-23Handle a few more userland traps that would lead to a kernel panic.kettenis1-2/+19
2020-12-22have the ifrxr info stuff report the buffer size the hw handles.dlg1-2/+2
2020-12-22Use SIGILL for the Facility Unavailable Interrupt in usermode.gkoehler1-1/+6
2020-12-22Add PCIe clocks.kettenis1-1/+5
2020-12-22For a while the kerrnel reports EACCES to userland if pf blocks abluhm1-3/+3
2020-12-22Implement select(2) and pselect(2) on top of kqueue.mpi1-55/+148
2020-12-22Defer hardware initialization in order to give things like PCIe PHYskettenis1-15/+31
2020-12-22Clear FSCR register. This gives us a sane default state where all facilitieskettenis2-2/+11
2020-12-22name the rx rings like ix does for systat mbdlg1-1/+2
2020-12-22Make clang the default compiler on loongson.visa1-2/+2
2020-12-22stop showing amd l3 cache informationjsg2-27/+3
2020-12-21Only enable rasops1_putchar8() and rasops1_putchar16() optomizations onkettenis1-5/+5
2020-12-20Accept reject and blackhole routes for IPsec PMTU discovery.bluhm4-10/+13
2020-12-20Fix typo.kettenis1-2/+2
2020-12-20The TCE table needs to be aligned on a boundary that is a multiple of itskettenis1-2/+2
2020-12-20Introduce klistopsvisa2-9/+173
2020-12-20Convert uvm_km_valloc(9) calls to km_alloc(9). Tested in qemu withjmatthew2-6/+8
2020-12-20sync with i915_pciids.hjsg1-2/+0
2020-12-20drm/i915: Remove dubious Valleyview PCI IDsjsg1-3/+1
2020-12-20remove duplicate device id caused by subids in INTEL_IVB_Q_IDSjsg1-1/+0
2020-12-20test against [VM_MIN_ADDRESS, VM_MAXUSER_ADDRESS] in access_ok()jsg1-3/+8
2020-12-19Apply r1.86 of amd64 acpi_machdep.c to arm64 and i386, converting a fewjmatthew2-6/+8
2020-12-19There's no need to include the OFW GPIO header.patrick1-2/+1
2020-12-19Add support for the i.MX8MP PCIe clocks.patrick2-1/+40
2020-12-18Add support for the i.MX8MP second ethernet. The Plus SoC not only has thepatrick2-4/+98
2020-12-18Emulate open drain GPIOs. This replaces the hack added in the last commit.kettenis1-31/+22
2020-12-18Add symbolic constants related to open source and open drain GPIOs.kettenis1-3/+10
2020-12-18Make large read and write transactions work.kettenis1-38/+58
2020-12-18Add glue for the USB3 controller on the i.MX8MP SoC. NXP had this glue forpatrick4-3/+84
2020-12-18Add code to initialize the USB 3 PHY on i.MX8MP.patrick1-2/+65
2020-12-18Add support for the i.MX8MP USB clocks.patrick2-2/+88
2020-12-18Attach imxgpc(4) to i.MX8MP as well.patrick1-1/+3
2020-12-18Add fd close notification for kqueue-based poll() and select()visa2-8/+40
2020-12-18Make knote_{activate,remove}() internal to kern_event.c.visa2-4/+4
2020-12-18Make sure the first packet of an SA has sequence number 1 (as described intobhe2-9/+11
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