linux-dev - Linux kernel development work

Age	Commit message (Collapse)	Author	Files	Lines
2020-11-16	dt-bindings: phy: Add Cadence Sierra PHY bindings in YAML format	Swapnil Jakhade	1	-70/+0
	Add Cadence Sierra PHY bindings in YAML format. Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1603898561-5142-1-git-send-email-sjakhade@cadence.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-01-08	dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E	Kishon Vijay Abraham I	1	-5/+8
	Add DT binding documentation for Sierra PHY IP used in TI's J721E SoC. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Rob Herring <robh@kernel.org>
2018-11-16	dt-bindings: phy: Document cadence Sierra PHY bindings	Alan Douglas	1	-0/+67
	Add DT binding documentation for Sierra PHY. The PHY supports a number of different protocols, including PCIe and USB. The PHY lanes may be configured as single or multi-lane links. Each link is treated as a separate sub-node. For example, if there are 4 lanes in total the first 2 might be configured as a multi-lane PCIe link while the other two are single lane USB links, and in this case there would be 3 sub-nodes. There are two resets for the PHY block (one for APB register access, one for the PHY link) and separate resets for each link. For multi-lane links, the reset corresponds to the reset line on the master lane, the resets on other lanes have no effect. Signed-off-by: Alan Douglas <adouglas@cadence.com> Signed-off-by: Rob Herring <robh@kernel.org>