linux-dev - Linux kernel development work

Age	Commit message (Collapse)	Author	Files	Lines
2022-08-25	dt-bindings: Remove 'Device Tree Bindings' from end of title:	Andrew Lunn	1	-1/+1
	As indicated in link: https://lore.kernel.org/all/20220822204945.GA808626-robh@kernel.org/ DT schema files should not have 'Device Tree Binding' as part of there title: line. Remove this in most .yaml files, so hopefully preventing developers copying it into new .yaml files, and being asked to remove it. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20220825020427.3460650-1-andrew@lunn.ch Signed-off-by: Rob Herring <robh@kernel.org>
2021-11-23	dt-bindings: phy: zynqmp-psgtr: fix USB phy name	Liam Beguin	1	-1/+1
	PHY_TYPE_USB is undefined and was added as PHY_TYPE_USB2 and PHY_TYPE_USB3 in 2fbbc96d1600 (phy: Add PHY header file for DT x Driver defines, 2014-11-04). Fix documentation to avoid misleading users. Signed-off-by: Liam Beguin <lvb@xiphos.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20211117003841.2030813-1-lvb@xiphos.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-07-01	dt-bindings: phy: zynqmp-psgtr: Fix example's numbers of cells in reg	Laurent Pinchart	1	-2/+2
	The DT examples are by default compiled in a parent that has #address-cells and #size-cells both set to 1. Fix the example accordingly, even if it doesn't match the actual hardware, as this is the recommended practice for DT bindings examples. Fixes: cea0f76a483d ("dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY") Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20200701134853.30656-1-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-06-29	dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY	Anurag Kumar Vulisha	1	-0/+105
	Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed Processing System Gigabit Transceiver which provides PHY capabilities to USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200629120054.29338-2-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul <vkoul@kernel.org>