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2022-04-13ARM: dts: rcar-gen2: Add interrupt properties to watchdog nodesWolfram Sang1-0/+1
Driver doesn't use it yet, but let's describe the HW properly. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20220322095512.4707-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-05-25ARM: dts: renesas: Move enable-method to CPU nodesGeert Uytterhoeven1-1/+2
According to Documentation/devicetree/bindings/arm/cpus.yaml, the "enable-method" property should be a property of the individual CPU nodes, and not of the parent "cpus" container node. However, on R-Car Gen2 and RZ/G1 SoCs, the property is tied to the "cpus" node instead. Secondary CPU bringup and CPU hot (un)plug work regardless, as arm_dt_init_cpu_maps() falls back to looking in the "cpus" node. The cpuidle code does not have such a fallback, so it does not detect the enable-method. Note that cpuidle does not support the "renesas,apmu" enable-method yet, so for now this does not make any difference. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/35fcfedf9de9269185c48ca5a6dfcba7cdd3484b.1621427319.git.geert+renesas@glider.be
2021-05-25ARM: dts: renesas: Add fck to etheravb-rcar-gen2 clock-names listAdam Ford1-0/+1
The bindings have been updated to support two clocks. Add a clock-names list in the device tree with fck in it. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20210224115146.9131-2-aford173@gmail.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2021-03-08ARM: dts: renesas: Group tuples in APMU cpus propertiesGeert Uytterhoeven1-1/+1
To improve human readability and enable automatic validation, the tuples in "cpus" properties in device nodes for Advanced Power Management Units for AP-System Core (APMU) should be grouped using angle brackets. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20210204130517.1647073-2-geert+renesas@glider.be
2020-09-11ARM: dts: renesas: Fix pin controller node namesGeert Uytterhoeven1-1/+1
According to Devicetree Specification v0.2 and later, Section "Generic Names Recommendation", the node name for a pin controller device node should be "pinctrl". Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200821112351.5518-1-geert+renesas@glider.be
2020-07-17ARM: dts: renesas: Fix SD Card/eMMC interface device node namesYoshihiro Shimoda1-1/+1
Fix the device node names as "mmc@". Fixes: 66474697923c ("ARM: dts: r7s72100: add sdhi to device tree") Fixes: a49f76cddaee ("ARM: dts: r7s9210: Add SDHI support") Fixes: 43304a5f5106 ("ARM: shmobile: r8a73a4: tidyup DT node naming") Fixes: 7d907894bfe3 ("ARM: shmobile: r8a7740: tidyup DT node naming") Fixes: 3ab2ea5fd1ce ("ARM: dts: r8a7742: Add SDHI nodes") Fixes: 63ce8a617b51 ("ARM: dts: r8a7743: Add SDHI controllers") Fixes: b591e323b271 ("ARM: dts: r8a7744: Add SDHI nodes") Fixes: d83010f87ab3 ("ARM: dts: r8a7744: Initial SoC device tree") Fixes: 7079131ef9b9 ("ARM: dts: r8a7745: Add SDHI controllers") Fixes: 0485da788028 ("ARM: dts: r8a77470: Add SDHI1 support") Fixes: 15aa5a95e820 ("ARM: dts: r8a77470: Add SDHI0 support") Fixes: f068cc816015 ("ARM: dts: r8a77470: Add SDHI2 support") Fixes: 14e1d9147d96 ("ARM: shmobile: r8a7778: tidyup DT node naming") Fixes: 2624705ceb7b ("ARM: shmobile: r8a7779: tidyup DT node naming") Fixes: b718aa448378 ("ARM: shmobile: r8a7790: tidyup DT node naming") Fixes: b7ed8a0dd4f1 ("ARM: shmobile: Add SDHI devices to r8a7791 DTSI") Fixes: ce01b14ecf19 ("ARM: dts: r8a7792: add SDHI support") Fixes: fc9ee228f500 ("ARM: dts: r8a7793: Add SDHI controllers") Fixes: b8e8ea127d00 ("ARM: shmobile: r8a7794: add SDHI DT support") Fixes: 33f6be3bf6b7 ("ARM: shmobile: sh73a0: tidyup DT node naming") Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/1594382936-14114-1-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-02-24ARM: dts: rcar-gen2: Add reset control properties for displayGeert Uytterhoeven1-2/+3
Add reset control properties to the device nodes for the Display Units on all supported R-Car Gen2 SoCs. Note that on these SoCs, there is only a single reset for all DU channels. Join the clocks lines while at it, to increase uniformity. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20200218133019.22299-2-geert+renesas@glider.be
2019-12-31ARM: dts: rcar-gen2: Add missing mmio-sram bus propertiesGeert Uytterhoeven1-0/+3
"#address-cells", "#size-cells", and "ranges" are required properties for devices nodes compatible with "mmio-sram", leading to warnings when running "make dtbs_check": $ make dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/sram/sram.yaml arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: sram@e63a0000: '#address-cells' is a required property arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: sram@e63a0000: '#size-cells' is a required property arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: sram@e63a0000: 'ranges' is a required property ... Fix this by adding the missing properties to the mmio-sram device nodes in the DTS files for all affected R-Car Gen2 and RZ/G1 SoCs. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191213162604.1890-1-geert+renesas@glider.be
2019-12-20ARM: dts: renesas: Group tuples in interrupt propertiesGeert Uytterhoeven1-32/+32
To improve human readability and enable automatic validation, the tuples in the various properties containing interrupt specifiers should be grouped. While "make dtbs_check" does not impose this yet for the "interrupts" property, it does for the "interrupt-map" property, leading to warnings like: pci@ee090000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 108, 4, 2048, 0, 0, 1, 5, 0, 108, 4, 4096, 0, 0, 2, 5, 0, 108, 4] is too long pci@ee0d0000: interrupt-map:0: [0, 0, 0, 1, 5, 0, 113, 4, 2048, 0, 0, 1, 5, 0, 113, 4, 4096, 0, 0, 2, 5, 0, 113, 4] is too long Fix this by grouping the tuples of the "interrupts" and "interrupt-map" properties using angle brackets. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20191213164115.3697-4-geert+renesas@glider.be Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
2019-06-21ARM: dts: r8a7792: Add CMT0 and CMT1 to r8a7792Magnus Damm1-0/+34
Add CMT0 and CMT1 to the R-Car Gen2 V2H (r8a7792) SoC. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2019-03-19ARM: dts: r8a7792: blanche: Add IIC3 and DA9063 PMIC nodeMarek Vasut1-0/+18
Add IIC3 node to R8A7792 SoC device tree and a DA9063 PMIC node to V2H Blanche board device tree. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-09-28ARM: dts: Include R-Car Gen2 product name in DTSI filesMagnus Damm1-1/+1
Improve the user friendliness of the DTS code base by including the R-Car product name in each R-Car Gen2 DTSI file. The product names are taken from: Documentation/devicetree/bindings/arm/shmobile.txt Signed-off-by: Magnus Damm <damm@opensource.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-08-27ARM: dts: rcar-gen2: Convert to new DU DT bindingsLaurent Pinchart1-1/+0
The DU DT bindings have been updated to drop the reg-names property. Update the r8a7792 and r8a7794 device trees accordingly. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-07-23ARM: dts: convert to SPDX identifier for Renesas boardsWolfram Sang1-4/+1
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-05-14ARM: dts: r8a7792: Add PMU device nodeGeert Uytterhoeven1-0/+7
Enable support for the ARM Performance Monitor Units in the Cortex-A15 CPU cores on R-Car V2H by adding a device node for the PMU. New Linux output: hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-04-25ARM: dts: r8a7792: Add RWDT nodeGeert Uytterhoeven1-0/+10
Add a device node for the Watchdog Timer (WDT) controller on the Renesas R-Car V2H (r8a7792) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-04-25ARM: dts: r8a7792: Adjust SMP routine sizeFabrizio Castro1-1/+1
This patch adjusts the definition of the SMP routine size according to the latest changes made by commit: "ARM: shmobile: Add watchdog support" Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2018-02-12ARM: dts: r8a7792: sort subnodes of soc nodeSimon Horman1-249/+249
Sort the subnodes of the soc node to improve maintainability. The sort key is the address on the bus with instances of the same IP block grouped together. This patch should not introduce any functional change. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-01-04Merge tag 'renesas-dt2-for-v4.16' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dtOlof Johansson1-34/+30
Second Round of Renesas ARM Based SoC DT Updates for v4.16 * r8a7745 (RZ/G1E) SoC - Enable SMP Fabrizio Castro says "Add DT node for the Advanced Power Management Unit (APMU), add the second CPU core, and use "renesas,apmu" as "enable-method"." * r8a7743 (RZ/G1M) SoC - Add node for thermal sensor module with thermal-zone support * r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs - Add: + Renesas Core Match Timer (CMT) support + Renesas Timer Pulse Unit PWM Controller (TPU) support + Renesas PWM Timer Controller (PWM) support * r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven and r8a7745 (RZ/G1E) iW-RainboW-G22D development platforms - Add sound support * r8a7743 (RZ/G1M), r8a7745 (RZ/G1E) and r8a7792 (R-Car V2H) SoCs - Allow DTBs of boards of these SoCs to build without any warnings when compiled with W=1 using gcc-linaro-5.4.1-2017.05 + Move nodes which have no reg property out of bus, they don't belong there + Also sort sub-nodes of root node to allow for easier maintenance * r8a7790 (R-Car H2), r8a7791 (R-Car M2-W) and r8a7793 (R-Car M2-N) SoCs - Correct critical CPU temperature Chris Paterson says "The current R-Car Gen2 device trees define the CPU critical temperature as 115°C. The R-Car hardware manuals state that Tc = –40°C to +105°C. The thermal sensor has an accuracy of ±5°C and there can be a temperature difference of 1 or 2 degrees between Tjmax and the thermal sensor due to the location of the latter. This means that 95°C is a safer value to use. This value should also apply to r8a7792 but thermal sensor support has not been added yet." * r8a7740 (R-Mobile A1) SoC - Correct TPU register block size Geert Uytterhoven says "The Timer Pulse Unit has registers that lie outside the declared register block. Enlarge the register block size to fix this. This was probably based on the old platform code, which also assumed a register block size of 0x100." * tag 'renesas-dt2-for-v4.16' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (37 commits) ARM: dts: r8a7745: Add missing clock for secondary CA7 CPU core ARM: dts: iwg22d-sodimm: Sound DMA support via DVC on DTS ARM: dts: iwg22d-sodimm: Sound DMA support via SRC on DTS ARM: dts: iwg22d-sodimm: Sound DMA support via BUSIF on DTS ARM: dts: iwg22d-sodimm: Sound DMA support on DTS ARM: dts: iwg22d-sodimm: Sound PIO support ARM: dts: iwg22d-sodimm: Enable SGTL5000 audio codec ARM: dts: r8a7745: Add sound support ARM: dts: r8a7745: Add audio DMAC support ARM: dts: r8a7745: Add audio clocks ARM: dts: r8a7740: Correct TPU register block size ARM: dts: r8a7743: move timer and thermal-zones nodes out of bus ARM: dts: r8a7743: sort root sub-nodes alphabetically ARM: dts: iwg20d-q7-common: Sound DMA support via DVC on DTS ARM: dts: iwg20d-q7-common: Sound DMA support via SRC on DTS ARM: dts: iwg20d-q7-common: Sound DMA support via BUSIF on DTS ARM: dts: iwg20d-q7-common: Sound DMA support on DTS ARM: dts: iwg20d-q7-common: Sound PIO support ARM: dts: iwg20d-q7-common: Enable SGTL5000 audio codec ARM: dts: r8a7792: move timer node out of bus ... Signed-off-by: Olof Johansson <olof@lixom.net>
2017-12-21Merge tag 'renesas-dt-for-v4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dtArnd Bergmann1-1/+2
Pull "Renesas ARM Based SoC DT Updates for v4.16" from Simon Horman: * Convert to named i2c-gpio bindings Geert Uytterhoeven says "Commits 7d29f509d2cfd807 ("dt-bindings: i2c: i2c-gpio: Add support for named gpios") and 05c74778858d7d99 ("i2c: gpio: Add support for named gpios in DT") introduced named i2c-gpio DT bindings, and deprecated the more error-prone unnamed variant. This patch series switches all Renesas boards to the new bindings, and adds the missing GPIO_OPEN_DRAIN I/O flags, which were implicitly assumed before..." ... Note that after this series is applied, the i2c-gpio buses are no longer detected when booting new DTBs on old (v4.14 and older) kernels, which should not be an issue. Booting old DTBs on new kernels is not affected." * Update DTS for CMT DT binding rework Geert Uytterhoeven says "This patch series updates the CMT device nodes in the various Renesas DTS files sh_cmt clocksource driver for the recent DT binding rework that was merged in v4.14-rc1 and v4.15-rc1..." * Add SMP support to r8a7794 (R-Car E2) SoC Sergei Shtylyov says "Add the device tree node for the Advanced Power Management Unit (APMU). Use the "enable-method" prop to point out that the APMU should be used for the SMP support." * Correct primary compatible value for eeprom on r7s72100 (RZ/A1H) genmai and r8a7791 (R-Car M2-W) koelsh boards Geert Uytterhoeven says "The Renesas part numbers of the two-wire serial interface EEPROMs do not follow the 24Cxx pattern, but the R1EX24xxx pattern. Hence change the primary compatible values to the appropriate variant of "renesas,r1ex24xxx", like is already done on Gose."" * Move cec_clock to root node on r8a7791 (R-Car M2-W) koelsh board r8a7791 (R-Car M2-W) koelsh board * Use R-Car SDHI and Ether Gen1 and 2 fallback compat strings Use recently posted R-Car SDHI and Ether Gen 1 and 2 fallback compat strings in the DT of Renesas ARM based SoCs. * Add IIC cores to dtsi of r8a7745 (RZ/G1E) SoC * Rework DT architecture for r8a7745 (RZ/G1E) iW-RainboW-G22D development platform and add serial support. Fabrizio Castro says "... define a new DT architecture for the iW-RainboW-G22D SODIMM Development Platform to include the configuration with the HDMI daughter board and to define the serial interfaces." * Add USB function support to r8a7745 (RZ/G1E) iW-RainboW-G22D development platform * Add PCIEC and ttySC3 support to r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven SoM * Add VIN support to r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs * Add CAN and HDMI support to r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven and r8a7745 (RZ/G1E) iW-RainboW-G22D development platforms * tag 'renesas-dt-for-v4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (61 commits) ARM: dts: alt: Convert to named i2c-gpio bindings ARM: dts: koelsch: Convert to named i2c-gpio bindings ARM: dts: lager: Convert to named i2c-gpio bindings ARM: dts: armadillo800eva: Convert to named i2c-gpio bindings ARM: dts: sh73a0: Remove CMT renesas,channels-mask ARM: dts: r8a7794: Remove CMT renesas,channels-mask ARM: dts: r8a7793: Remove CMT renesas,channels-mask ARM: dts: r8a7791: Remove CMT renesas,channels-mask ARM: dts: r8a7790: Remove CMT renesas,channels-mask ARM: dts: r8a7740: Remove CMT renesas,channels-mask ARM: dts: r8a73a4: Remove CMT renesas,channels-mask ARM: dts: r8a7794: Update CMT compat strings ARM: dts: r8a7793: Update CMT compat strings ARM: dts: r8a7791: Update CMT compat strings ARM: dts: r8a7790: Update CMT compat strings ARM: dts: r8a73a4: Update CMT compat string ARM: dts: r8a7794: Add SMP support ARM: dts: genmai: Correct primary compatible value for eeprom ARM: dts: koelsch: Correct primary compatible value for eeprom ARM: dts: r8a7745: add VIN dt support ...
2017-12-20ARM: dts: r8a7792: move timer node out of busSimon Horman1-12/+8
The timer node does not have any register properties and thus shouldn't be placed on the bus. This problem is flagged by the compiler as follows: $ make dtbs W=1 ... DTC arch/arm/boot/dts/r8a7792-wheat.dtb arch/arm/boot/dts/r8a7792-blanche.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property arch/arm/boot/dts/r8a7792-wheat.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-12-20ARM: dts: r8a7792: sort root sub-nodes alphabeticallySimon Horman1-24/+24
Sort root sub-nodes alphabetically to allow for easier maintenance of this file. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-11-27ARM: dts: r8a7792: Use R-Car SDHI Gen2 fallback compat stringSimon Horman1-1/+2
Use newly added R-Car SDHI Gen2 fallback compat string in the DT of the r8a7792 SoC. This should have no run-time effect as the driver matches against the per-SoC compat string before considering the fallback compat string. Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-11-20ARM: dts: r8a779x: Add '#reset-cells' in cpg-mssrArnd Bergmann1-0/+1
With the latest dtc, we get many warnings about the missing '#reset-cells' property in these controllers, e.g.: arch/arm/boot/dts/r8a7790-lager.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /can@e6e80000:resets[0]) arch/arm/boot/dts/r8a7792-blanche.dtb: Warning (resets_property): Missing property '#reset-cells' in node /soc/clock-controller@e6150000 or bad phandle (referred from /soc/dma-controller@e6700000:resets[0]) arch/arm/boot/dts/r8a7792-wheat.dtb: Warning (resets_property): Missing property '#reset-cells' in node /soc/clock-controller@e6150000 or bad phandle (referred from /soc/ethernet@e6800000:resets[0]) arch/arm/boot/dts/r8a7793-gose.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /gpio@e6050000:resets[0]) arch/arm/boot/dts/r8a7794-alt.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /i2c@e6500000:resets[0]) arch/arm/boot/dts/r8a7794-silk.dtb: Warning (resets_property): Missing property '#reset-cells' in node /clock-controller@e6150000 or bad phandle (referred from /interrupt-controller@e61c0000:resets[0]) This adds it for the three r8a779x chips that were lacking it. The binding mandates this as <1>, so this is the value I use. Signed-off-by: Arnd Bergmann <arnd@arndb.de> [geert: Add fix for r8a7793.dtsi] Fixes: 34fbd2b12761d111 ("ARM: dts: r8a7790: Add reset control properties") Fixes: 6e11a322f1d7505d ("ARM: dts: r8a7792: Add reset control properties") Fixes: 84fb19e1d201ba86 ("ARM: dts: r8a7793: Add reset control properties") Fixes: 615beb759ca494a4 ("ARM: dts: r8a7794: Add reset control properties") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-16ARM: dts: r8a7792: Add missing clock for secondary CA15 CPU coreGeert Uytterhoeven1-0/+1
Currently only the primary CPU in the CA15 cluster has a clocks property, while the secondary CPU core is driven by the same clock. Add the missing clocks property to fix this. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-10-16ARM: dts: r8a7792: Use R-Car GPIO Gen2 fallback compat stringSimon Horman1-12/+12
Use newly added R-Car GPIO Gen2 fallback compat string in place of now deprecated non-generation specific R-Car GPIO fallback compat string in the DT of the r8a7792 SoC. This should have no run-time effect as the driver matches against the per-SoC compat string before considering the fallback compat string. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-10-06ARM: dts: r8a7792: Use generic node name for VSP1 nodesGeert Uytterhoeven1-3/+3
Use the preferred generic node name instead of the specific name. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-19ARM: dts: r8a7792: Add reset control propertiesGeert Uytterhoeven1-0/+45
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, but audio is not yet enabled in r8a7792.dtsi, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-09-18ARM: dts: r8a7792: Convert to new CPG/MSSR bindingsGeert Uytterhoeven1-272/+61
Convert the R-Car V2H SoC from the old "Renesas R-Car Gen2 Clock Pulse Generator (CPG)" and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. This simplifies the DTS files, and allows to add support for reset control later. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-07-27ARM: dts: r8a7792: Reserve SRAM for the SMP jump stubGeert Uytterhoeven1-0/+8
Reserve SRAM for the jump stub for CPU core bringup. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-07-27ARM: dts: r8a7792: Add Inter Connect RAMGeert Uytterhoeven1-0/+10
R-Car V2H has 2 regions of Inter Connect RAM (72 + 4 KiB). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-04-03ARM: dts: r8a7792: Correct Z clockGeert Uytterhoeven1-2/+9
Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a fixed divider. This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2. Hence: - Remove the Z clock output from the cpg_clocks node, as this implied a programmable clock, - Add the Z clock as a fixed factor clock, - Let the first CPU node point to the new Z clock, - Remove the Z clock index from the bindings (this definition was used by r8a7792.dtsi only, and was not a contract between DT and driver). Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-03-10ARM: dts: r8a7792: Add INTC-SYS clock to device treeGeert Uytterhoeven1-3/+8
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always on" PM Domain, so it can be power managed using that clock. Note that currently the GIC-400 driver doesn't support module clocks nor Runtime PM, so this must be handled as a critical clock. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-03-07ARM: dts: r8a7792: Remove unit-address and reg from integrated cacheGeert Uytterhoeven1-2/+1
The Cortex-A15 cache controller is an integrated controller, and thus the device node representing it should not have a unit-addresses or reg property. Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2017-02-07ARM: DTS: Fix register map for virt-capable GICMarc Zyngier1-1/+1
Since everybody copied my own mistake from the DT binding example, let's address all the offenders in one swift go. Most of them got the CPU interface size wrong (4kB, while it should be 8kB), except for both keystone platforms which got the control interface wrong (4kB instead of 8kB). In a few cases where I knew for sure what implementation was used, I've added the "arm,gic-400" compatible string. I'm 99% sure that this is what everyone is using, but short of having the TRM for all the other SoCs, I've left them alone. Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2017-01-03ARM: dts: r8a7792: Use R-Car Gen 2 fallback binding for msiof nodesSimon Horman1-2/+4
Use recently added R-Car Gen 2 fallback binding for msiof nodes in DT for r8a7792 SoC. This has no run-time effect for the current driver as the initialisation sequence is the same for the SoC-specific binding for r8a7792 and the fallback binding for R-Car Gen 2. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-01-03ARM: dts: r8a7792: Use R-Car Gen 2 fallback binding for i2c nodesSimon Horman1-6/+12
Use recently added R-Car Gen 2 fallback binding for i2c nodes in DT for r8a7792 SoC. This has no run-time effect for the current driver as the initialisation sequence is the same for the SoC-specific binding for r8a7792 and the fallback binding for R-Car Gen 2. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-12-15Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-2/+54
Pull ARM DT updates from Arnd Bergmann: "Lots of changes as usual, so I'm trying to be brief here. Most of the new hardware support has the respective driver changes merged through other trees or has had it available for a while, so this is where things come together. We get a DT descriptions for a couple of new SoCs, all of them variants of other chips we already support, and usually coming with a new evaluation board: - Oxford semiconductor (now Broadcom) OX820 SoC for NAS devices - Qualcomm MDM9615 LTE baseband - NXP imx6ull, the latest and smallest i.MX6 application processor variant - Renesas RZ/G (r8a7743 and r8a7745) application processors - Rockchip PX3, a variant of the rk3188 chip used in Android tablets - Rockchip rk1108 single-core application processor - ST stm32f746 Cortex-M7 based microcontroller - TI DRA71x automotive processors These are commercially available consumer platforms we now support: - Motorola Droid 4 (xt894) mobile phone - Rikomagic MK808 Android TV stick based on Rockchips rx3066 - Cloud Engines PogoPlug v3 based on OX820 - Various Broadcom based wireless devices: - Netgear R8500 router - Tenda AC9 router - TP-LINK Archer C9 V1 - Luxul XAP-1510 Access point - Turris Omnia open hardware router based on Armada 385 And a couple of new boards targeted at developers, makers or industrial integration: - Macnica Sodia development platform for Altera socfpga (Cyclone V) - MicroZed board based on Xilinx Zynq FPGA platforms - TOPEET itop/elite based on exynos4412 - WP8548 MangOH Open Hardware platform for IOT, based on Qualcomm MDM9615 - NextThing CHIP Pro gadget - NanoPi M1 development board - AM571x-IDK industrial board based on TI AM5718 - i.MX6SX UDOO Neo - Boundary Devices Nitrogen6_SOM2 (i.MX6) - Engicam i.CoreM6 - Grinn i.MX6UL liteSOM/liteBoard - Toradex Colibri iMX6 module Other changes: - added peripherals on renesas, davinci, stm32f429, uniphier, sti, mediatek, integrator, at91, imx, vybrid, ls1021a, omap, qualcomm, mvebu, allwinner, broadcom, exynos, zynq - Continued fixes for W=1 dtc warnings - The old STiH415/416 SoC support gets removed, these never made it into products and have served their purpose in the kernel as a template for teh newer chips from ST - The exynos4415 dtsi file is removed as nothing uses it. - Intel PXA25x can now be booted using devicetree" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (422 commits) arm: dts: zynq: Add MicroZed board support ARM: dts: da850: enable high speed for mmc ARM: dts: da850: Add node for pullup/pulldown pinconf ARM: dts: da850: enable memctrl and mstpri nodes per board ARM: dts: da850-lcdk: Add ethernet0 alias to DT ARM: dts: artpec: add pcie support ARM: dts: add support for Turris Omnia devicetree: Add vendor prefix for CZ.NIC ARM: dts: berlin2q-marvell-dmp: fix typo in chosen node ARM: dts: berlin2q-marvell-dmp: fix regulators' name ARM: dts: Add xo to sdhc clock node on qcom platforms ARM: dts: r8a7794: Add device node for PRR ARM: dts: r8a7793: Add device node for PRR ARM: dts: r8a7792: Add device node for PRR ARM: dts: r8a7791: Add device node for PRR ARM: dts: r8a7790: Add device node for PRR ARM: dts: r8a7779: Add device node for PRR ARM: dts: r8a73a4: Add device node for PRR ARM: dts: sk-rzg1e: add Ether support ARM: dts: sk-rzg1e: initial device tree ...
2016-11-23ARM: dts: r8a7792: Add device node for PRRGeert Uytterhoeven1-0/+5
Add a device node for the Product Register, which provides SoC product and revision information. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-11-04ARM: dts: r8a7792: add MSIOF supportSergei Shtylyov1-0/+30
Define the generic R8A7792 parts of the MSIOF0/1 device nodes. Based on the original (and large) patch by Vladimir Barinov <vladimir.barinov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-11-04ARM: dts: r8a7792: add MSIOF clocksSergei Shtylyov1-2/+19
Describe the MSIOF0/1 clocks and their parent, MP clock in the R8A7792 device tree. Based on the original (and large) patch by Vladimir Barinov <vladimir.barinov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-11-02ARM: dts: r8a7792: Add device node for RST moduleGeert Uytterhoeven1-0/+5
Add a device node for the RST module, which provides a.o. reset control and mode pin monitoring. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-05ARM: dts: r8a7792: add QSPI supportSergei Shtylyov1-0/+16
Define the generic R8A7792 part of the QSPI device node. Based on the original (and large) patch by Vladimir Barinov <vladimir.barinov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-09-05ARM: dts: r8a7792: add QSPI clockSergei Shtylyov1-2/+5
Describe the QSPI clock in the R8A7792 device tree. Based on the original (and large) patch by Vladimir Barinov <vladimir.barinov@cogentembedded.com>. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-23ARM: dts: r8a7792: add VSP1V supportSergei Shtylyov1-0/+24
Describe 3 instances (VSPS, VSPD0, and VSPD1) of the VSP1V in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-23ARM: dts: r8a7792: add VSP1V clocksSergei Shtylyov1-3/+8
Describe the VSP1V clocks in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-09ARM: dts: r8a7792: add DU supportSergei Shtylyov1-0/+28
Define the generic R8A7792 part of the DU device node. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-09ARM: dts: r8a7792: add DU clocksSergei Shtylyov1-2/+11
Describe the DU0/1 clocks and their parent, ZX clock in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-09ARM: dts: r8a7792: fix misindented lineSergei Shtylyov1-1/+1
Commit 2a0900655d5e (ARM: dts: r8a7792: add I2C support) had a wrongly indented line at the end of the "aliases" subnode -- fix it. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-08-09ARM: dts: r8a7792: add VIN supportSergei Shtylyov1-0/+66
Define the generic R8A7792 parts of the VIN[0-5] device nodes. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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