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2019-12-11arm64: dts: ls1088a: Add QSPI support for NXP LS1088Ashish Kumar1-0/+24
Add QSPI node in dtsi(ls1088a), and dts(ls1088ardb, ls1088aqds) boards. Both ls1088ardb and ls1088aqds has two 64MB flash from SPANSION(s25fs512s). QUAD I/O is tested in case of read and single I/O is tested in case of write. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-24arm64: dts: ls1088a-qds: Add the spi-flash nodes under the DSPI controllerChuanhua Han1-0/+33
This patch adds the spi-flash nodes under the DSPI controller for ls1088a-qds boards. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2018-06-19arm64: dts: freescale: Update to use SPDX identifiersLi Yang1-37/+1
Replace license text with corresponding SPDX identifiers and update the format of existing SPDX identifiers to follow the new guideline Documentation/process/license-rules.rst. Note that some of the files mentioned X11 license previously but the license text actually matches MIT license. Signed-off-by: Li Yang <leoyang.li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-15arm64: dts: Add flash node for ls1088a qds and rdbPrabhakar Kushwaha1-0/+24
LS1088AQDS consist of NOR, NAND and FPGA connected over IFC LS1088ARDB consist of NAND and FPGA connected over IFC. So add flash information in ifc node of device tree. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-05-15arm64: dts: ls1088a: add esdhc nodeYangbo Lu1-0/+4
Add esdhc node for ls1088a and enable it on both RDB and QDS boards. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2017-03-29arm64: dts: Add support for FSL's LS1088A SoCHarninder Rai1-0/+123
LS1088A contains eight ARM v8 CortexA53 processor cores with 32 KB L1-D cache and 32 KB L1-I cache Features summary Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs - Arranged as two clusters of four cores sharing a 1 MB L2 cache - Speed Up to 1.5 GHz - Support for cluster power-gating. Cache coherent interconnect (CCI-400) - Hardware-managed data coherency - Up to 700 MHz One 64-bit DDR4 SDRAM memory controller with ECC Data path acceleration architecture 2.0 (DPAA2) Three PCIe 3.0 controllers One serial ATA (SATA 3.0) controller Three high-speed USB 3.0 controllers with integrated PHY Following levels of DTSI/DTS files have been created for the LS1088A SoC family: - fsl-ls1088a.dtsi: DTS-Include file for NXP LS1088A SoC. - fsl-ls1088a-qds.dts: DTS file for NXP LS1088A QDS board. - fsl-ls1088a-rdb.dts: DTS file for NXP LS1088A RDB board Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>` Signed-off-by: Shawn Guo <shawnguo@kernel.org>