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2022-06-16arm64: dts: microchip: adjust whitespace around '='Krzysztof Kozlowski2-124/+124
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220526204110.831805-1-krzysztof.kozlowski@linaro.org
2022-04-26arm64: dts: microchip: align SPI NOR node name with dtschemaKrzysztof Kozlowski4-7/+7
The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220407143223.295344-2-krzysztof.kozlowski@linaro.org
2022-03-04dts: sparx5: Enable ptp interruptHoratiu Vultur1-2/+3
Add support for ptp interrupt. This interrupt is used when using 2-step timestamping. For each timestamp that is added in a queue, an interrupt is generated. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-08-20arm64: dts: sparx5: Add the Sparx5 switch frame DMA supportSteen Hegelund1-2/+3
This adds the interrupt for the Sparx5 Frame DMA. If this configuration is present the Sparx5 SwitchDev driver will use the Frame DMA feature, and if not it will use register based injection and extraction for sending and receiving frames to the CPU. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2021-06-24arm64: dts: sparx5: Add the Sparx5 switch nodeSteen Hegelund3-84/+1112
This provides the configuration for the currently available evaluation boards PCB134 and PCB135. The series depends on the following series currently on its way into the kernel: - Sparx5 Reset Driver Link: https://lore.kernel.org/r/20210416084054.2922327-1-steen.hegelund@microchip.com/ Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2020-12-10arm64: dts: sparx5: Add SGPIO devicesLars Povlsen4-0/+409
This adds SGPIO devices for the Sparx5 SoC and configures it for the applicable reference boards. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20201113145151.68900-4-lars.povlsen@microchip.com
2020-12-10arm64: dts: sparx5: Add reset supportLars Povlsen1-0/+5
This adds reset support to the Sparx5 SoC DT. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20201006200316.2261245-4-lars.povlsen@microchip.com
2020-09-16arm64: dts: sparx5: Add spi-nand devicesLars Povlsen5-0/+67
This patch add spi-nand DT nodes to the applicable Sparx5 boards. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200824203010.2033-7-lars.povlsen@microchip.com
2020-09-16arm64: dts: sparx5: Add spi-nor supportLars Povlsen3-0/+80
This add spi-nor device nodes to the Sparx5 reference boards. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200824203010.2033-6-lars.povlsen@microchip.com
2020-09-16arm64: dts: sparx5: Add SPI controller and associated mmio-muxLars Povlsen1-0/+30
This adds a SPI controller to the Microchip Sparx5 SoC, as well as the mmio-mux that is required to select the right SPI interface for a given SPI device. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200824203010.2033-4-lars.povlsen@microchip.com
2020-09-16arm64: dts: sparx5: Add hwmon temperature sensorLars Povlsen1-0/+7
This adds a hwmon temperature node sensor to the Sparx5 SoC. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200618135951.25441-3-lars.povlsen@microchip.com
2020-09-16arm64: dts: sparx5: Add Sparx5 eMMC supportLars Povlsen4-0/+93
This adds eMMC support to the applicable Sparx5 board configuration files. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200825081357.32354-4-lars.povlsen@microchip.com
2020-07-28arm64: dts: sparx5: Add i2c devices, i2c muxesLars Povlsen5-0/+360
This patch adds i2c devices and muxes to the Sparx5 reference boards. Link: https://lore.kernel.org/r/20200615133242.24911-11-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-28arm64: dts: sparx5: Add Sparx5 SoC DPLL clockLars Povlsen1-16/+23
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller. Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.com Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-22arm64: dts: sparx5: Add pinctrl supportLars Povlsen3-0/+36
This add pinctrl support to the Microchip Sparx5 SoC. Link: https://lore.kernel.org/r/20200615133242.24911-5-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2020-07-22arm64: dts: sparx5: Add basic cpu supportLars Povlsen10-0/+266
This adds the basic DT structure for the Microchip Sparx5 SoC, and the reference boards, pcb125, pcb134 and pcb135. The two latter have a NAND vs a eMMC centric variant (as a mount option). Link: https://lore.kernel.org/r/20200615133242.24911-4-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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