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path: root/drivers/gpu/drm/i915/i915_reg.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2021-09-24drm/i915/fbc: Align FBC segments to 512B on glk+Ville Syrjälä1-0/+4
2021-09-20drm/i915/dg2: add DG2+ TRANS_DDI_FUNC_CTL DP 2.0 128b/132b modeJani Nikula1-1/+1
2021-09-17drm/i915/display/adlp: Add new PSR2 workaroundsJosé Roberto de Souza1-0/+4
2021-09-01drm/i915/dsi/xelpd: Add WA to program LP to HS wakeup guardbandVandita Kulkarni1-0/+8
2021-08-30drm/i915/display: Drop PSR support from HSW and BDWJosé Roberto de Souza1-16/+5
2021-08-30drm/i915/dg2: UHBR tables added for pll programmingAnimesh Manna1-0/+4
2021-08-24drm/i915/dg2: add TRANS_DP2_VFREQHIGH and TRANS_DP2_VFREQLOWJani Nikula1-0/+14
2021-08-24drm/i915/dg2: add TRANS_DP2_CTL register definitionJani Nikula1-0/+9
2021-08-20drm/i915/fbc: Polish the skl+ FBC stride override handlingVille Syrjälä1-2/+3
2021-08-16Merge drm/drm-next into drm-intel-nextJani Nikula1-1/+47
2021-08-12Merge tag 'drm-intel-next-2021-08-10-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-nextDave Airlie1-201/+185
2021-08-12Merge tag 'drm-intel-gt-next-2021-08-06-1' of ssh://git.freedesktop.org/git/drm/drm-intel into drm-nextDave Airlie1-1/+47
2021-08-11drm/i915/display: Fix the 12 BPC bits for PIPE_MISC regAnkit Nautiyal1-5/+11
2021-08-05drm/i915/dg2: Add SQIDI steeringMatt Roper1-0/+2
2021-08-05drm/i915/xehp: handle new steering optionsDaniele Ceraolo Spurio1-0/+3
2021-08-03drm/i915/xehp: Changes to ss/eu definitionsMatthew Auld1-0/+3
2021-08-03drm/i915/guc/slpc: Sysfs hooks for SLPCVinay Belgaumkar1-0/+2
2021-08-03drm/i915/guc/slpc: Cache platform frequency limitsVinay Belgaumkar1-0/+3
2021-08-02drm/i915: Correct SFC_DONE register offsetMatt Roper1-1/+1
2021-07-30drm/i915: rename/remove CNL registersLucas De Marchi1-145/+47
2021-07-30drm/i915: rename CNL references in intel_dram.cLucas De Marchi1-12/+12
2021-07-30drm/i915: remove explicit CNL handling from intel_pm.cLucas De Marchi1-1/+1
2021-07-30drm/i915: remove explicit CNL handling from i915_irq.cLucas De Marchi1-1/+1
2021-07-30drm/i915/display: rename CNL references in skl_scaler.cLucas De Marchi1-2/+2
2021-07-30drm/i915/display: remove explicit CNL handling from intel_display_power.cLucas De Marchi1-13/+0
2021-07-30drm/i915/display: remove explicit CNL handling from intel_dpll_mgr.cLucas De Marchi1-2/+2
2021-07-30drm/i915/display: remove explicit CNL handling from intel_cdclk.cLucas De Marchi1-2/+2
2021-07-29drm/i915/dg2: Update lane disable power state during PSRGwan-gyeong Mun1-0/+3
2021-07-29drm/i915/dg2: Wait for SNPS PHY calibration during display initMatt Roper1-0/+1
2021-07-29drm/i915/dg2: Add vswing programming for SNPS physMatt Roper1-0/+5
2021-07-29drm/i915/dg2: Add MPLLB programming for HDMIMatt Roper1-0/+3
2021-07-29drm/i915/dg2: Add MPLLB programming for SNPS PHYMatt Roper1-0/+56
2021-07-28drm/i915/adlp: Add workaround to disable CMTG clock gatingImre Deak1-0/+3
2021-07-27drm/i915/adl_p: Allow underrun recovery when possibleMatt Roper1-1/+2
2021-07-27drm/i915/guc: Provide mmio list to be saved/restored on engine resetJohn Harrison1-0/+1
2021-07-27drm/i915: Implement PSF GV point supportStanislav Lisovskiy1-1/+5
2021-07-27drm/i915: Extend QGV point restrict mask to 0x3Stanislav Lisovskiy1-1/+1
2021-07-26drm/i915/gt: nuke gen6_hw_idLucas De Marchi1-1/+10
2021-07-24drm/i915/xehp: Extra media engines - Part 3 (reset)John Harrison1-0/+8
2021-07-24drm/i915/xehp: Extra media engines - Part 2 (interrupts)John Harrison1-0/+3
2021-07-24drm/i915/xehp: Extra media engines - Part 1 (engine definitions)John Harrison1-0/+6
2021-07-23drm/i915: Program chicken bit during DP MST sequence on TGL+Matt Roper1-9/+10
2021-07-22drm/i915/gt: rename legacy engine->hw_id to engine->gen6_hw_idLucas De Marchi1-1/+1
2021-07-22drm/i915/guc: Implement GuC context operations for new intefaceMatthew Brost1-0/+1
2021-07-22drm/i915/xehp: Handle new device context ID formatStuart Summers1-0/+5
2021-07-22drm/i915: Fork DG1 interrupt handlerPaulo Zanoni1-2/+2
2021-07-20drm/i915/display/adl_p: Implement PSR changesJosé Roberto de Souza1-10/+16
2021-07-09drm/i915/dg1: Compute MEM Bandwidth using MCHBARClint Taylor1-0/+12
2021-07-06drm/i915/display/dg1: Correctly map DPLLs during state readoutJosé Roberto de Souza1-3/+0
2021-07-01drm/i915/display/dg1: Correctly map DPLLs during state readoutJosé Roberto de Souza1-3/+0
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