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path: root/drivers/gpu/drm/i915/i915_reg.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2019-11-05drm/i915/gen8+: Add RC6 CTX corruption WAImre Deak1-0/+2
2019-11-05drm/i915: Lower RM timeout to avoid DSI hard hangsUma Shankar1-0/+4
2019-11-05drm/i915: Add gen9 BCS cmdparsingJon Bloomfield1-0/+4
2019-08-20drm/i915/tgl: Updated Private PAT programmingMichel Thierry1-0/+1
2019-08-16drm/i915: Move gmbus definitions out of i915_reg.hDaniele Ceraolo Spurio1-21/+1
2019-08-16drm/i915: Move engine IDs out of i915_reg.hDaniele Ceraolo Spurio1-24/+3
2019-08-16drm/i915: Move i915_power_well_id out of i915_reg.hDaniele Ceraolo Spurio1-21/+0
2019-08-13drm/i915: Add _TRANS2()José Roberto de Souza1-3/+4
2019-08-13drm/i915/tgl: Fix missing parentheses on TGL_TRANS_DDI_FUNC_CTL_VAL_TO_PORTJosé Roberto de Souza1-1/+1
2019-08-08drm/i915/tgl: Fix the read of the DDI that transcoder is attached toJosé Roberto de Souza1-0/+2
2019-08-08drm/i915/tgl/dsi: Enable blanking packets during BLLP for video modeVandita Kulkarni1-0/+1
2019-08-01drm/i915/tgl: Add and use new DC5 and DC6 residency counter registersJosé Roberto de Souza1-0/+2
2019-07-31drm/i915/tgl: Tigerlake only has global MOCS registersMichel Thierry1-0/+2
2019-07-31drm/i915/tgl: Move fault registers to their new offsetLucas De Marchi1-0/+3
2019-07-30drm/i915/tgl: handle DP aux interruptsLucas De Marchi1-0/+3
2019-07-30drm/i915/tgl: Update north display hotplug detection to TGL connectionsJosé Roberto de Souza1-2/+10
2019-07-30drm/i915/tgl: Add hpd interrupt handlingLucas De Marchi1-1/+27
2019-07-26drm/i915/tgl: update ddi/tc clock_off bitsMahesh Kumar1-2/+3
2019-07-26drm/i915/tgl: select correct bit for port selectMahesh Kumar1-3/+8
2019-07-19drm/i915/icl: Add Wa_1409178092Tvrtko Ursulin1-0/+3
2019-07-13drm/i915/guc: unify guc irq handlingDaniele Ceraolo Spurio1-10/+0
2019-07-12drm/i915: Add modular FIAAnusha Srivatsa1-4/+9
2019-07-12drm/i915: Add test for invalid flag bits in whitelist entriesJohn Harrison1-3/+9
2019-07-11drm/i915/tgl: Update DPLL clock reference registerJosé Roberto de Souza1-0/+1
2019-07-11drm/i915/tgl: Add DPLL registersLucas De Marchi1-0/+17
2019-07-11drm/i915/tgl: Add gmbus gpio pin to port mappingMahesh Kumar1-1/+3
2019-07-11drm/i915/tgl: apply Display WA #1178 to fix type C donglesLucas De Marchi1-1/+3
2019-07-11drm/i915/tgl: Add power well to support 4th pipeMika Kahola1-0/+1
2019-07-11drm/i915/tgl: Add power well supportImre Deak1-1/+19
2019-07-11drm/i915/tgl: Check if pipe D is fusedJosé Roberto de Souza1-0/+1
2019-07-11drm/i915: Add 4th pipe and transcoderLucas De Marchi1-0/+3
2019-07-10drm/i915/gen11: Convert combo PHY logic to use new 'enum phy' namespaceMatt Roper1-37/+37
2019-07-10drm/i915/gen11: Program ICL_DPCLKA_CFGCR0 according to PHYMatt Roper1-4/+8
2019-07-10Merge drm/drm-next into drm-intel-next-queuedRodrigo Vivi1-3/+3
2019-07-05drm/i915: Program plane gamma rampsVille Syrjälä1-7/+24
2019-07-05drm/i915: Disable sprite gamma on ivb-bdwVille Syrjälä1-1/+1
2019-07-01drm/i915/ehl: Add third combo PHY offsetMatt Roper1-1/+3
2019-06-21Merge tag 'drm-intel-next-2019-06-19' of git://anongit.freedesktop.org/drm/drm-intel into drm-nextDave Airlie1-20/+70
2019-06-20drm/i915/ehl/dsi: Enable AFE over PPI strapJosé Roberto de Souza1-0/+4
2019-06-20drm/i915/ehl/dsi: Set lane latency optimization for DW1Vandita Kulkarni1-0/+2
2019-06-19drm/i915/ehl: Allow combo PHY A to drive a third external displayMatt Roper1-0/+1
2019-06-19Merge v5.2-rc5 into drm-nextDaniel Vetter1-3/+4
2019-06-18drm/i915: Support flags in whitlist WAsJohn Harrison1-0/+7
2019-06-17drm/i915/icl: Add register definitions for Multi Segmented gammaUma Shankar1-1/+18
2019-06-14drm/i915: Add Wa_1409120013:icl,ehlMatt Roper1-0/+1
2019-06-12drm/i915: Improve WRPLL reference clock readout on HSW/BDWVille Syrjälä1-0/+3
2019-06-12drm/i915: Rename HSW/BDW PLL bitsVille Syrjälä1-12/+20
2019-06-12drm/i915: Do not touch the PCH SSC reference if a PLL is using itVille Syrjälä1-0/+1
2019-06-12drm/i915/perf: fix whitelist on Gen10+Lionel Landwerlin1-0/+1
2019-06-10drm/i915/perf: fix whitelist on Gen10+Lionel Landwerlin1-0/+1
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