fpga: Add option to specify build output directory

7 files changed, 138 insertions, 127 deletions

diff --git a/fpga/usrp3/tools/make/viv_design_builder.mak b/fpga/usrp3/tools/make/viv_design_builder.mak
index cd2f0e332..f10268124 100644
--- a/fpga/usrp3/tools/make/viv_design_builder.mak
+++ b/fpga/usrp3/tools/make/viv_design_builder.mak
@@ -30,7 +30,7 @@ BUILD_VIVADO_DESIGN = \
 	export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
 	export VIV_INCR_BUILD=$(INCR_BUILD); \
 	cd $(BUILD_DIR); \
-	$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(BUILD_DIR)/../dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
+	$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(MAKEFILE_DIR)/dev_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou
 
 
 # -------------------------------------------------------------------
diff --git a/fpga/usrp3/tools/make/viv_preamble.mak b/fpga/usrp3/tools/make/viv_preamble.mak
index ea2bd92fd..8db631b64 100644
--- a/fpga/usrp3/tools/make/viv_preamble.mak
+++ b/fpga/usrp3/tools/make/viv_preamble.mak
@@ -27,7 +27,10 @@ SIMLIB_DIR = $(abspath $(BASE_DIR)/../sim)
 LIB_IP_DIR = $(abspath $(LIB_DIR)/ip)
 HLS_IP_DIR = $(abspath $(LIB_DIR)/hls)
 
-BUILD_BASE_DIR ?= .
+MAKEFILE_DIR = $(abspath .)
+
+IP_BUILD_DIR ?= $(abspath ./build-ip/$(subst /,,$(PART_ID)))
+BUILD_BASE_DIR ?= $(abspath .)
 
 ifdef NAME
 BUILD_DIR = $(abspath $(BUILD_BASE_DIR)/build-$(NAME))
@@ -35,7 +38,6 @@ else
 BUILD_DIR = $(abspath $(BUILD_BASE_DIR)/build)
 endif
 
-IP_BUILD_DIR = $(abspath ./build-ip/$(subst /,,$(PART_ID)))
 
 # -------------------------------------------------------------------
 # Git Hash Retrieval
diff --git a/fpga/usrp3/top/e31x/Makefile b/fpga/usrp3/top/e31x/Makefile
index ee2966173..09e03939a 100644
--- a/fpga/usrp3/top/e31x/Makefile
+++ b/fpga/usrp3/top/e31x/Makefile
@@ -10,12 +10,14 @@
 ## make <Targets> <Options>
 ##
 ##Output:
-## build/usrp_<product>_fpga_<image_type>.bit:    Configuration bitstream with header
-## build/usrp_<product>_fpga_<image_type>.dts:    Device tree source file
-## build/usrp_<product>_fpga_<image_type>.rpt:    Build report (includes utilization and timing summary)
+## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit:    Configuration bitstream with header
+## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.dts:    Device tree source file
+## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.rpt:    Build report (includes utilization and timing summary)
 
-# Base output directory for all builds
+# Base output directory for all builds.
 BUILD_BASE_DIR ?= .
+# Base directory for the build outputs.
+BUILD_OUTPUT_DIR ?= $(BUILD_BASE_DIR)/build
 
 # Initialize a build seed. This can be changed to randomly affect build results.
 BUILD_SEED ?= 0
@@ -45,11 +47,11 @@ vivado_ip    = make -f Makefile.e31x.inc viv_ip    NAME=$@ ARCH=$(XIL_ARCH_$1) P
 # post_build($1=Device, $2=Option)
 ifeq ($(TARGET),bin)
 	post_build = @\
-		mkdir -p build; \
+		mkdir -p $(BUILD_OUTPUT_DIR); \
 		echo "Exporting bitstream file..."; \
-		cp $(BUILD_BASE_DIR)/build-$(1)/e31x.bit build/usrp_`echo $(2) | tr A-Z a-z`_fpga.bit; \
+		cp $(BUILD_BASE_DIR)/build-$(1)/e31x.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(2) | tr A-Z a-z`_fpga.bit; \
 		echo "Exporting build report..."; \
-		cp $(BUILD_BASE_DIR)/build-$(1)/build.rpt build/usrp_`echo $(2) | tr A-Z a-z`_fpga.rpt; \
+		cp $(BUILD_BASE_DIR)/build-$(1)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(2) | tr A-Z a-z`_fpga.rpt; \
 		echo "Build DONE ... $(1)";
 else
 	post_build = @echo "Skipping bitfile export."
@@ -70,40 +72,39 @@ E310_SG3_IP:
 	+$(call vivado_ip,E310_SG3,E310_SG3=1)
 
 ##E310_SG1_IDLE:  Build USRP E3XX idle design (Speed Grade 1).
-E310_SG1_IDLE E3XX_idle: E310_SG1_IP build/usrp_e310_sg1_idle_fpga.dts
+E310_SG1_IDLE E3XX_idle: E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_idle_fpga.dts
 	$(call vivado_build,E310_SG1,$(DEFS) E310_IDLE_IMAGE=1 E310_SG1=1)
 	$(call post_build,$@,E310_SG1_IDLE)
 
 ##E310_SG3_IDLE:  Build USRP E3XX idle design (Speed Grade 3).
-E310_SG3_IDLE E3XX_idle_sg3: E310_SG3_IP build/usrp_e310_sg3_idle_fpga.dts
+E310_SG3_IDLE E3XX_idle_sg3: E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_idle_fpga.dts
 	$(call vivado_build,E310_SG3,$(DEFS) E310_IDLE_IMAGE=1 E310_SG3=1)
 	$(call post_build,$@,E310_SG3_IDLE)
 
 ##E310_SG1:       Build USRP E3XX (Speed Grade 1).
-E310_SG1 E310: E310_SG1_IP build/usrp_e310_sg1_fpga.dts
+E310_SG1 E310: E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_fpga.dts
 	$(call vivado_build,E310_SG1,$(DEFS) E310_SG1=1 $(if $(DRAM),ENABLE_DRAM=1,))
 	$(call post_build,$@,E310_SG1)
 
 ##E310_SG3:       Build USRP E3XX (Speed Grade 3).
-E310_SG3 E310_sg3: E310_SG3_IP build/usrp_e310_sg3_fpga.dts
+E310_SG3 E310_sg3: E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_fpga.dts
 	$(call vivado_build,E310_SG3,$(DEFS) E310_SG3=1 $(if $(DRAM),ENABLE_DRAM=1,))
 	$(call post_build,$@,E310_SG3)
 
-
-build/%.dts: dts/%.dts dts/*.dtsi
-	-mkdir -p build
+$(BUILD_OUTPUT_DIR)/%.dts: dts/%.dts dts/*.dtsi
+	-mkdir -p $(BUILD_OUTPUT_DIR)
 	${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
 
 clean:          ##Clean up all target build outputs.
 	@echo "Cleaning targets..."
-	@rm -rf build-E3*
-	@rm -rf build
+	@rm -rf $(BUILD_BASE_DIR)/build-E3*
+	@rm -rf $(BUILD_OUTPUT_DIR)
 
 cleanall:       ##Clean up all target and ip build outputs.
 	@echo "Cleaning targets and IP..."
 	@rm -rf build-ip
-	@rm -rf build-E3*
-	@rm -rf build
+	@rm -rf $(BUILD_BASE_DIR)/build-E3*
+	@rm -rf $(BUILD_OUTPUT_DIR)
 
 help:           ##Show this help message.
 	@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
diff --git a/fpga/usrp3/top/e320/Makefile b/fpga/usrp3/top/e320/Makefile
index f12045638..0dbbbb417 100644
--- a/fpga/usrp3/top/e320/Makefile
+++ b/fpga/usrp3/top/e320/Makefile
@@ -10,12 +10,14 @@
 ## make <Targets> <Options>
 ##
 ##Output:
-## build/usrp_<product>_fpga_<image_type>.bit:    Configuration bitstream with header
-## build/usrp_<product>_fpga_<image_type>.dts:    Device tree source file
-## build/usrp_<product>_fpga_<image_type>.rpt:    Build report (includes utilization and timing summary)
+## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit:    Configuration bitstream with header
+## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.dts:    Device tree source file
+## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.rpt:    Build report (includes utilization and timing summary)
 
-# Base output directory for all builds
+# Base output directory for all builds.
 BUILD_BASE_DIR ?= .
+# Base directory for the build outputs.
+BUILD_OUTPUT_DIR ?= $(BUILD_BASE_DIR)/build
 
 # Initialize a build seed. This can be changed to randomly affect build results.
 BUILD_SEED ?= 0
@@ -48,11 +50,11 @@ vivado_ip    = make -f Makefile.e320.inc viv_ip    NAME=$@ ARCH=$(XIL_ARCH_$1) P
 # post_build($1=Device, $2=Option)
 ifeq ($(TARGET),bin)
 	post_build = @\
-		mkdir -p build; \
+		mkdir -p $(BUILD_OUTPUT_DIR); \
 		echo "Exporting bitstream file..."; \
-		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/e320.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
+		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/e320.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
 		echo "Exporting build report..."; \
-		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
+		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
 		echo "Build DONE ... $(1)_$(2)";
 else
 	post_build = @echo "Skipping bitfile export."
@@ -69,35 +71,34 @@ E320_IP:
 	+$(call vivado_ip,E320,$(XG_DEFS) E320=1)
 
 ##E320_1G:  1GigE on SFP+ Port.
-E320_1G: E320_IP build/usrp_e320_fpga_1G.dts
+E320_1G: E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_1G.dts
 	$(call vivado_build,E320,$(1G_DEFS) E320=1)
 	$(call post_build,E320,1G)
 
 ##E320_XG:  10GigE on SFP+ Port.
-E320_XG: E320_IP build/usrp_e320_fpga_XG.dts
+E320_XG: E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_XG.dts
 	$(call vivado_build,E320,$(XG_DEFS) E320=1)
 	$(call post_build,E320,XG)
 
 ##E320_AA:  Aurora on SFP+ Port.
-E320_AA: E320_IP build/usrp_e320_fpga_AA.dts
+E320_AA: E320_IP $(BUILD_OUTPUT_DIR)/usrp_e320_fpga_AA.dts
 	$(call vivado_build,E320,$(AA_DEFS) E320=1)
 	$(call post_build,E320,AA)
 
-
-build/%.dts: dts/%.dts dts/*.dtsi
-	-mkdir -p build
+$(BUILD_OUTPUT_DIR)/%.dts: dts/%.dts dts/*.dtsi
+	-mkdir -p $(BUILD_OUTPUT_DIR)
 	${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
 
 clean:    ##Clean up all target build outputs.
 	@echo "Cleaning targets..."
-	@rm -rf build-E3*_*
-	@rm -rf build
+	@rm -rf $(BUILD_BASE_DIR)/build-E3*_*
+	@rm -rf $(BUILD_OUTPUT_DIR)
 
 cleanall: ##Clean up all target and ip build outputs.
 	@echo "Cleaning targets and IP..."
 	@rm -rf build-ip
-	@rm -rf build-E3*_*
-	@rm -rf build
+	@rm -rf $(BUILD_BASE_DIR)/build-E3*_*
+	@rm -rf $(BUILD_OUTPUT_DIR)
 
 help:     ##Show this help message.
 	@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
diff --git a/fpga/usrp3/top/n3xx/Makefile b/fpga/usrp3/top/n3xx/Makefile
index 5525af8f0..8896eaa2e 100644
--- a/fpga/usrp3/top/n3xx/Makefile
+++ b/fpga/usrp3/top/n3xx/Makefile
@@ -11,9 +11,9 @@
 ## make <Targets> <Options>
 ##
 ##Output:
-## build/usrp_<product>_fpga_<image_type>.bit:    Configuration bitstream with header
-## build/usrp_<product>_fpga_<image_type>.dts:    Device tree source file
-## build/usrp_<product>_fpga_<image_type>.rpt:    Build report (includes utilization and timing summary)
+## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit:    Configuration bitstream with header
+## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.dts:    Device tree source file
+## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.rpt:    Build report (includes utilization and timing summary)
 
 # Debug Options
 # Uncomment this line or add to make arg to omit radio_clk (sourced from db) and use bus_clk as radio_clk
@@ -23,8 +23,10 @@
 # Uncomment this line to add four example Aurora loopback lanes on the QSFP NPIO bus.
 # OPTIONS += QSFP_LANES=4
 
-# Base output directory for all builds
+# Base output directory for all builds.
 BUILD_BASE_DIR ?= .
+# Base directory for the build outputs.
+BUILD_OUTPUT_DIR ?= $(BUILD_BASE_DIR)/build
 
 # Initialize a build seed. This can be changed to randomly affect build results.
 BUILD_SEED ?= 0
@@ -71,11 +73,11 @@ vivado_ip    = make -f Makefile.n3xx.inc viv_ip    NAME=$@ ARCH=$(XIL_ARCH_$1) P
 # post_build($1=Device, $2=Option)
 ifeq ($(TARGET),bin)
 	post_build = @\
-		mkdir -p build; \
+		mkdir -p $(BUILD_OUTPUT_DIR); \
 		echo "Exporting bitstream file..."; \
-		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/n3xx.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
+		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/n3xx.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
 		echo "Exporting build report..."; \
-		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
+		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
 		echo "Build DONE ... $(1)_$(2)";
 else
 	post_build = @echo "Skipping bitfile export."
@@ -98,109 +100,109 @@ N3X0_IP:
 	+$(call vivado_ip,N310,$(HG_DEFS) N310=1,$(N310_DEFAULTS))
 
 ##N310_WX:  1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1.
-N310_WX: N3X0_IP build/usrp_n310_fpga_WX.dts
+N310_WX: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_WX.dts
 	$(call vivado_build,N310,$(WX_DEFS) N310=1,$(N310_DEFAULTS))
 	$(call post_build,N310,WX)
 
 ##N310_HG:  1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
-N310_HG: N3X0_IP build/usrp_n310_fpga_HG.dts
+N310_HG: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_HG.dts
 	$(call vivado_build,N310,$(HG_DEFS) N310=1,$(N310_DEFAULTS))
 	$(call post_build,N310,HG)
 
 ##N310_XG:  10GigE on SFP+ Port0, 10Gig on SFP+ Port1.
-N310_XG: N3X0_IP build/usrp_n310_fpga_XG.dts
+N310_XG: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_XG.dts
 	$(call vivado_build,N310,$(XG_DEFS) N310=1,$(N310_DEFAULTS))
 	$(call post_build,N310,XG)
 
 ##N310_HA:  1Gig on SFP+ Port0, Aurora on SFP+ Port1.
-N310_HA: N3X0_IP build/usrp_n310_fpga_HA.dts
+N310_HA: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_HA.dts
 	$(call vivado_build,N310,$(HA_DEFS) N310=1,$(N310_DEFAULTS))
 	$(call post_build,N310,HA)
 
 ##N310_XA:  10Gig on SFP+ Port0, Aurora on SFP+ Port1.
-N310_XA: N3X0_IP build/usrp_n310_fpga_XA.dts
+N310_XA: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_XA.dts
 	$(call vivado_build,N310,$(XA_DEFS) N310=1,$(N310_DEFAULTS))
 	$(call post_build,N310,XA)
 
 ##N310_AA:  Aurora on SFP+ Port0, Aurora on SFP+ Port1.
-N310_AA: N3X0_IP build/usrp_n310_fpga_AA.dts
+N310_AA: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n310_fpga_AA.dts
 	$(call vivado_build,N310,$(AA_DEFS) N310=1,$(N310AA_DEFAULTS))
 	$(call post_build,N310,AA)
 
 ##N300_WX:  1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1.
-N300_WX: N300_IP build/usrp_n300_fpga_WX.dts
+N300_WX: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_WX.dts
 	$(call vivado_build,N300,$(WX_DEFS) N300=1,$(N300_DEFAULTS))
 	$(call post_build,N300,WX)
 
 ##N300_HG:  1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
-N300_HG: N300_IP build/usrp_n300_fpga_HG.dts
+N300_HG: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_HG.dts
 	$(call vivado_build,N300,$(HG_DEFS) N300=1,$(N300_DEFAULTS))
 	$(call post_build,N300,HG)
 
 ##N300_XG:  10GigE on SFP+ Port0, 10Gig on SFP+ Port1.
-N300_XG: N300_IP build/usrp_n300_fpga_XG.dts
+N300_XG: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_XG.dts
 	$(call vivado_build,N300,$(XG_DEFS) N300=1,$(N300_DEFAULTS))
 	$(call post_build,N300,XG)
 
 ##N300_HA:  1Gig on SFP+ Port0, Aurora on SFP+ Port1.
-N300_HA: N300_IP build/usrp_n300_fpga_HA.dts
+N300_HA: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_HA.dts
 	$(call vivado_build,N300,$(HA_DEFS) N300=1,$(N300_DEFAULTS))
 	$(call post_build,N300,HA)
 
 ##N300_XA:  10Gig on SFP+ Port0, Aurora on SFP+ Port1.
-N300_XA: N300_IP build/usrp_n300_fpga_XA.dts
+N300_XA: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_XA.dts
 	$(call vivado_build,N300,$(XA_DEFS) N300=1,$(N300_DEFAULTS))
 	$(call post_build,N300,XA)
 
 ##N300_AA:  Aurora on SFP+ Port0, Aurora on SFP+ Port1.
-N300_AA: N300_IP build/usrp_n300_fpga_AA.dts
+N300_AA: N300_IP $(BUILD_OUTPUT_DIR)/usrp_n300_fpga_AA.dts
 	$(call vivado_build,N300,$(AA_DEFS) N300=1,$(N300AA_DEFAULTS))
 	$(call post_build,N300,AA)
 
 ##N320_WX:  1GigE White Rabbit on SFP+ Port0, 10Gig on SFP+ Port1.
-N320_WX: N3X0_IP build/usrp_n320_fpga_WX.dts
+N320_WX: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_WX.dts
 	$(call vivado_build,N320,$(WX_DEFS) N320=1,$(N320_DEFAULTS))
 	$(call post_build,N320,WX)
 
 ##N320_HG:  1GigE on SFP+ Port0, 10Gig on SFP+ Port1.
-N320_HG: N3X0_IP build/usrp_n320_fpga_HG.dts
+N320_HG: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_HG.dts
 	$(call vivado_build,N320,$(HG_DEFS) N320=1,$(N320_DEFAULTS))
 	$(call post_build,N320,HG)
 
 ##N320_XG:  10GigE on SFP+ Port0, 10Gig on SFP+ Port1.
-N320_XG: N3X0_IP build/usrp_n320_fpga_XG.dts
+N320_XG: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_XG.dts
 	$(call vivado_build,N320,$(XG_DEFS) N320=1,$(N320_DEFAULTS))
 	$(call post_build,N320,XG)
 
 ##N320_XQ:  WR on SFP+ Port0, 10Gig on QSFP+ Port0,1.
-N320_XQ: N3X0_IP build/usrp_n320_fpga_XQ.dts
+N320_XQ: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_XQ.dts
 	$(call vivado_build,N320,$(XQ_DEFS) N320=1,$(N320_DEFAULTS))
 	$(call post_build,N320,XQ)
 
 ##N320_AQ:  10Gig on SFP+ Port0,1 Aurora on QSFP+ Port0,1,2,3.
-N320_AQ: N3X0_IP build/usrp_n320_fpga_AQ.dts
+N320_AQ: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_AQ.dts
 	$(call vivado_build,N320,$(AQ_DEFS) N320=1,$(N320_DEFAULTS))
 	$(call post_build,N320,AQ)
 
 ##N320_AA:  Aurora on SFP+ Port0, Aurora on SFP+ Port1.
-N320_AA: N3X0_IP build/usrp_n320_fpga_AA.dts
+N320_AA: N3X0_IP $(BUILD_OUTPUT_DIR)/usrp_n320_fpga_AA.dts
 	$(call vivado_build,N320,$(AA_DEFS) N320=1,$(N320AA_DEFAULTS))
 	$(call post_build,N320,AA)
 
-build/%.dts: dts/%.dts dts/*.dtsi
-	-mkdir -p build
+$(BUILD_OUTPUT_DIR)/%.dts: dts/%.dts dts/*.dtsi
+	-mkdir -p $(BUILD_OUTPUT_DIR)
 	${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
 
 clean:    ##Clean up all target build outputs.
 	@echo "Cleaning targets..."
-	@rm -rf build-N3*_*
-	@rm -rf build
+	@rm -rf $(BUILD_BASE_DIR)/build-N3*_*
+	@rm -rf $(BUILD_OUTPUT_DIR)
 
 cleanall: ##Clean up all target and ip build outputs.
 	@echo "Cleaning targets and IP..."
 	@rm -rf build-ip
-	@rm -rf build-N3*_*
-	@rm -rf build
+	@rm -rf $(BUILD_BASE_DIR)/build-N3*_*
+	@rm -rf $(BUILD_OUTPUT_DIR)
 
 help:     ##Show this help message.
 	@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
diff --git a/fpga/usrp3/top/x300/Makefile b/fpga/usrp3/top/x300/Makefile
index 82e1d77ee..d7550a09d 100644
--- a/fpga/usrp3/top/x300/Makefile
+++ b/fpga/usrp3/top/x300/Makefile
@@ -10,10 +10,10 @@
 ## make <Targets> <Options>
 ##
 ##Output:
-## build/usrp_<product>_fpga_<image_type>.bit:    Configuration bitstream with header
-## build/usrp_<product>_fpga_<image_type>.bin:    Configuration bitstream without header
-## build/usrp_<product>_fpga_<image_type>.lvbitx: Configuration bitstream for PCIe (NI-RIO)
-## build/usrp_<product>_fpga_<image_type>.rpt:    Build report (includes utilization and timing summary)
+## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit:    Configuration bitstream with header
+## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bin:    Configuration bitstream without header
+## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.lvbitx: Configuration bitstream for PCIe (NI-RIO)
+## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.rpt:    Build report (includes utilization and timing summary)
 
 # Debug Options
 # Uncomment the following line to add a debug UART on GPIO 10 & 11
@@ -21,8 +21,10 @@
 
 CREATE_LVBITX=python3 ../../lib/io_port2/create-lvbitx.py
 
-# Base output directory for all builds
+# Base output directory for all builds.
 BUILD_BASE_DIR ?= .
+# Base directory for the build outputs.
+BUILD_OUTPUT_DIR ?= $(BUILD_BASE_DIR)/build
 
 # Initialize a build seed. This can be changed to randomly affect build results.
 BUILD_SEED ?= 0
@@ -59,15 +61,15 @@ vivado_ip    = make -f Makefile.x300.inc viv_ip    NAME=$@ ARCH=$(XIL_ARCH_$1) P
 # post_build($1=Device, $2=Option)
 ifeq ($(TARGET),bin)
 	post_build = @\
-		mkdir -p build; \
+		mkdir -p $(BUILD_OUTPUT_DIR); \
 		echo "Exporting bitstream files..."; \
-		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/x300.bin build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bin; \
-		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/x300.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
+		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/x300.bin $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bin; \
+		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/x300.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
 		echo "Generating LVBITX..."; \
-		$(CREATE_LVBITX) --input-bin=$(BUILD_BASE_DIR)/build-$(1)_$(2)/x300.bin --output-lvbitx=build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
-		cp -f x3x0_base.lvbitx build/`echo $(1) | tr A-Z a-z`.lvbitx_base; \
+		$(CREATE_LVBITX) --input-bin=$(BUILD_BASE_DIR)/build-$(1)_$(2)/x300.bin --output-lvbitx=$(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).lvbitx --device="USRP $(1)" x3x0_base.lvbitx; \
+		cp -f x3x0_base.lvbitx $(BUILD_OUTPUT_DIR)/`echo $(1) | tr A-Z a-z`.lvbitx_base; \
 		echo "Exporting build report..."; \
-		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
+		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
 		echo "Build DONE ... $(1)_$(2)";
 else
 	post_build = @echo "Skipping bitfile export."
@@ -139,14 +141,14 @@ X300_XA: X300_IP
 
 clean:    ##Clean up all target build outputs.
 	@echo "Cleaning targets..."
-	@rm -rf build-X3*_*
-	@rm -rf build
+	@rm -rf $(BUILD_BASE_DIR)/build-X3*_*
+	@rm -rf $(BUILD_OUTPUT_DIR)
 
 cleanall: ##Clean up all target and ip build outputs.
 	@echo "Cleaning targets and IP..."
 	@rm -rf build-ip
-	@rm -rf build-X3*_*
-	@rm -rf build
+	@rm -rf $(BUILD_BASE_DIR)/build-X3*_*
+	@rm -rf $(BUILD_OUTPUT_DIR)
 
 help:     ##Show this help message.
 	@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
diff --git a/fpga/usrp3/top/x400/Makefile b/fpga/usrp3/top/x400/Makefile
index 81ea87b02..424984658 100644
--- a/fpga/usrp3/top/x400/Makefile
+++ b/fpga/usrp3/top/x400/Makefile
@@ -12,12 +12,15 @@
 ##  make <Targets> <Options>
 ##
 ##Output:
-##  build/usrp_<product>_fpga_<image_type>.bit:  Configuration bitstream with header
-##  build/usrp_<product>_fpga_<image_type>.dts:  Device tree source file
-##  build/usrp_<product>_fpga_<image_type>.rpt:  Build report (includes utilization and timing summary)
+##  $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit:  Configuration bitstream with header
+##  $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.dts:  Device tree source file
+##  $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.rpt:  Build report (includes utilization and timing summary)
 
-# Base output directory for all builds
+
+# Base output directory for all builds.
 BUILD_BASE_DIR ?= .
+# Base directory for the build outputs.
+BUILD_OUTPUT_DIR ?= $(BUILD_BASE_DIR)/build
 
 # Definitions
 # MGT Types from x4xx_mgt_type.vh
@@ -118,11 +121,11 @@ vivado_ip    = make -f Makefile.x4xx.inc viv_ip    NAME=$@ ARCH=$(XIL_ARCH_$1) P
 # vivado_build($1=Device, $2=Option)
 ifeq ($(TARGET),bin)
 	post_build = @\
-		mkdir -p build; \
+		mkdir -p $(BUILD_OUTPUT_DIR); \
 		echo "Exporting bitstream file..."; \
-		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/x4xx.bit build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
+		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/x4xx.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).bit; \
 		echo "Exporting build report..."; \
-		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt build/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
+		cp $(BUILD_BASE_DIR)/build-$(1)_$(2)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(1) | tr A-Z a-z`_fpga_$(2).rpt; \
 		echo "Build DONE ... $(1)_$(2)";
 else
 	post_build = @echo "Skipping bitfile export."
@@ -162,111 +165,111 @@ endif
 ##* Note: Not all targets are shipped with UHD
 ##* Note: Some YAML configurations might not use all available DRAM channels.
 
-X410_X1_100: X410_IP build/usrp_x410_fpga_X1_100.dts
+X410_X1_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X1_100.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
 	$(call post_build,X410,X1_100)
 
-X410_XG_100: X410_IP build/usrp_x410_fpga_XG_100.dts
+X410_XG_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_XG_100.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
 	$(call post_build,X410,XG_100)
 
-X410_X4_100: X410_IP build/usrp_x410_fpga_X4_100.dts
+X410_X4_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X4_100.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
 	$(call post_build,X410,X4_100)
 
-X410_X4C_100: X410_IP build/usrp_x410_fpga_X4C_100.dts
+X410_X4C_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X4C_100.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_X4C_200_DEFAULTS))
 	$(call post_build,X410,X4C_100)
 
-X410_C1_100: X410_IP build/usrp_x410_fpga_C1_100.dts
+X410_C1_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_C1_100.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
 	$(call post_build,X410,C1_100)
 
-X410_UC_100: X410_IP build/usrp_x410_fpga_UC_100.dts
+X410_UC_100: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_UC_100.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
 	$(call post_build,X410,UC_100)
 
-X410_X1_200: X410_IP build/usrp_x410_fpga_X1_200.dts
+X410_X1_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X1_200.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
 	$(call post_build,X410,X1_200)
 
-X410_XG_200: X410_IP build/usrp_x410_fpga_XG_200.dts
+X410_XG_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_XG_200.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
 	$(call post_build,X410,XG_200)
 
-X410_X4_200: X410_IP build/usrp_x410_fpga_X4_200.dts
+X410_X4_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X4_200.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_200_DEFAULTS))
 	$(call post_build,X410,X4_200)
 
-X410_X4C_200: X410_IP build/usrp_x410_fpga_X4C_200.dts
+X410_X4C_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X4C_200.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_X4C_200_DEFAULTS))
 	$(call post_build,X410,X4C_200)
 
-X410_C1_200: X410_IP build/usrp_x410_fpga_C1_200.dts
+X410_C1_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_C1_200.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
 	$(call post_build,X410,C1_200)
 
-X410_UC_200: X410_IP build/usrp_x410_fpga_UC_200.dts
+X410_UC_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_UC_200.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
 	$(call post_build,X410,UC_200)
 
-X410_X1_400: X410_IP build/usrp_x410_fpga_X1_400.dts
+X410_X1_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X1_400.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
 	$(call post_build,X410,X1_400)
 
-X410_XG_400: X410_IP build/usrp_x410_fpga_XG_400.dts
+X410_XG_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_XG_400.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
 	$(call post_build,X410,XG_400)
 
-X410_X4_400: X410_IP build/usrp_x410_fpga_X4_400.dts
+X410_X4_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_X4_400.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_D_DEFAULTS))
 	$(call post_build,X410,X4_400)
 
-X410_C1_400: X410_IP build/usrp_x410_fpga_C1_400.dts
+X410_C1_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_C1_400.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
 	$(call post_build,X410,C1_400)
 
-X410_UC_400: X410_IP build/usrp_x410_fpga_UC_400.dts
+X410_UC_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_UC_400.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
 	$(call post_build,X410,UC_400)
 
-X410_CG_400: X410_IP build/usrp_x410_fpga_CG_400.dts
+X410_CG_400: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_CG_400.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_400_DEFAULTS))
 	$(call post_build,X410,CG_400)
 
-X440_X4_200: X440_IP build/usrp_x440_fpga_X4_200.dts
+X440_X4_200: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_X4_200.dts
 	$(call vivado_build,X440,$(DEFS) X440=1,$(X440_200_DEFAULTS))
 	$(call post_build,X440,X4_200)
 
-X440_X1_400: X440_IP build/usrp_x440_fpga_X1_400.dts
+X440_X1_400: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_X1_400.dts
 	$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_D_DEFAULTS))
 	$(call post_build,X440,X1_400)
 
-X440_X4_400: X440_IP build/usrp_x440_fpga_X4_400.dts
+X440_X4_400: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_X4_400.dts
 	$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_D_DEFAULTS))
 	$(call post_build,X440,X4_400)
 
-X440_C1_400: X440_IP build/usrp_x440_fpga_C1_400.dts
+X440_C1_400: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_C1_400.dts
 	$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_DEFAULTS))
 	$(call post_build,X440,C1_400)
 
-X440_CG_400: X440_IP build/usrp_x440_fpga_CG_400.dts
+X440_CG_400: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_CG_400.dts
 	$(call vivado_build,X440,$(DEFS) X440=1,$(X440_400_DEFAULTS))
 	$(call post_build,X440,CG_400)
 
-X440_X1_1600: X440_IP build/usrp_x440_fpga_X1_1600.dts
+X440_X1_1600: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_X1_1600.dts
 	$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_D_DEFAULTS))
 	$(call post_build,X440,X1_1600)
 
-X440_X4_1600: X440_IP build/usrp_x440_fpga_X4_1600.dts
+X440_X4_1600: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_X4_1600.dts
 	$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_D_DEFAULTS))
 	$(call post_build,X440,X4_1600)
 
-X440_C1_1600: X440_IP build/usrp_x440_fpga_C1_1600.dts
+X440_C1_1600: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_C1_1600.dts
 	$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_DEFAULTS))
 	$(call post_build,X440,C1_1600)
 
-X440_CG_1600: X440_IP build/usrp_x440_fpga_CG_1600.dts
+X440_CG_1600: X440_IP $(BUILD_OUTPUT_DIR)/usrp_x440_fpga_CG_1600.dts
 	$(call vivado_build,X440,$(DEFS) X440=1,$(X440_1600_DEFAULTS))
 	$(call post_build,X440,CG_1600)
 
@@ -277,7 +280,7 @@ X440_CG_1600: X440_IP build/usrp_x440_fpga_CG_1600.dts
 ##-------------|-----------|----|-----------------|-----------------|------------
 ##X410_CG_200  | 200       | 4  | 100 GbE         | 100 GbE         | 64b x 4 Ch
 
-X410_CG_200: X410_IP build/usrp_x410_fpga_CG_200.dts
+X410_CG_200: X410_IP $(BUILD_OUTPUT_DIR)/usrp_x410_fpga_CG_200.dts
 	$(call vivado_build,X410,$(DEFS) X410=1,$(X410_CG_200_DEFAULTS))
 	$(call post_build,X410,CG_200)
 
@@ -295,8 +298,8 @@ X410_IP:      ##Build IP only.
 X440_IP:      ##Build IP only.
 	+$(call vivado_ip,X440,$(DEFS) X440=1)
 
-build/usrp_x410%.dts: dts/*.dts dts/*.dtsi
-	-mkdir -p build
+$(BUILD_OUTPUT_DIR)/usrp_x410%.dts: dts/*.dts dts/*.dtsi
+	-mkdir -p $(BUILD_OUTPUT_DIR)
 	tools/parse_versions_for_dts.py \
 		--input regmap/x410/versioning_regs_regmap_utils.vh \
 		--output dts/x410-version-info.dtsi \
@@ -304,8 +307,8 @@ build/usrp_x410%.dts: dts/*.dts dts/*.dtsi
 	${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
 		$$(python3 tools/get_dts_input.py --target $@)
 
-build/usrp_x440%.dts: dts/*.dts dts/*.dtsi
-	-mkdir -p build
+$(BUILD_OUTPUT_DIR)/usrp_x440%.dts: dts/*.dts dts/*.dtsi
+	-mkdir -p $(BUILD_OUTPUT_DIR)
 	tools/parse_versions_for_dts.py \
 		--input regmap/x440/versioning_regs_regmap_utils.vh \
 		--output dts/x440-version-info.dtsi \
@@ -315,14 +318,14 @@ build/usrp_x440%.dts: dts/*.dts dts/*.dtsi
 
 clean:        ##Clean up all target build outputs.
 	@echo "Cleaning targets..."
-	@rm -rf build-X4*
-	@rm -rf build
+	@rm -rf $(BUILD_BASE_DIR)/build-X4*
+	@rm -rf $(BUILD_OUTPUT_DIR)
 
 cleanall:     ##Clean up all target and IP build outputs.
 	@echo "Cleaning targets and IP..."
 	@rm -rf build-ip
-	@rm -rf build-X4*
-	@rm -rf build
+	@rm -rf $(BUILD_BASE_DIR)/build-X4*
+	@rm -rf $(BUILD_OUTPUT_DIR)
 
 help:         ##Show this help message.
 	@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'