ci: use fpga pipeline artifacts for x4xx testing

8 files changed, 92 insertions, 0 deletions

diff --git a/.ci/templates/stages-uhd-pipeline.yml b/.ci/templates/stages-uhd-pipeline.yml
index 18a7713f7..de47c4310 100644
--- a/.ci/templates/stages-uhd-pipeline.yml
+++ b/.ci/templates/stages-uhd-pipeline.yml
@@ -444,20 +444,30 @@ stages:
   - template: tests/job-uhd-x410-hardware-tests-sdr-test0.yml
     parameters:
       testOS: ubuntu1804
+      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
   - template: tests/job-uhd-x440-hardware-tests-sdr-test0.yml
     parameters:
       testOS: ubuntu1804
+      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
   - template: tests/job-uhd-x410-hardware-tests-pebbles.yml
     parameters:
       testOS: ubuntu1804
+      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       testLength: ${{ parameters.testLength }}
   - template: tests/job-uhd-x440-hardware-tests-pebbles.yml
     parameters:
       testOS: ubuntu1804
+      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       testLength: ${{ parameters.testLength }}
   - template: tests/job-uhd-x440-hardware-tests-saison.yml
     parameters:
       testOS: ubuntu2204
+      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       extra_rf_test_args: --test_selector test_rx_phase_coherence.py test_tx_phase_coherence.py
       testLength: ${{ parameters.testLength }}
 
diff --git a/.ci/templates/tests/job-uhd-x410-hardware-tests-pebbles.yml b/.ci/templates/tests/job-uhd-x410-hardware-tests-pebbles.yml
index b838f8fc0..d9a1d3f55 100644
--- a/.ci/templates/tests/job-uhd-x410-hardware-tests-pebbles.yml
+++ b/.ci/templates/tests/job-uhd-x410-hardware-tests-pebbles.yml
@@ -6,6 +6,10 @@ parameters:
 - name: uhdArtifactSource
   type: string
   default: current
+- name: uhdFpgaArtifactSource
+  type: string
+- name: fpga_imgs_source
+  type: string
 - name: extra_rf_test_args
   type: string
   default: ''
@@ -22,6 +26,8 @@ jobs:
     runDevTest: false
     runSystemImageTest: false
     uhdArtifactSource: ${{ parameters.uhdArtifactSource }}
+    uhdFpgaArtifactSource: ${{ parameters.uhdFpgaArtifactSource }}
+    fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
     xilinxLocation: /opt/Xilinx/Vivado/2019.1
     extra_rf_test_args: '${{ parameters.extra_rf_test_args }}'
     testLength: '${{ parameters.testLength }}'
diff --git a/.ci/templates/tests/job-uhd-x410-hardware-tests-sdr-test0.yml b/.ci/templates/tests/job-uhd-x410-hardware-tests-sdr-test0.yml
index 13e577ee9..af91d8257 100644
--- a/.ci/templates/tests/job-uhd-x410-hardware-tests-sdr-test0.yml
+++ b/.ci/templates/tests/job-uhd-x410-hardware-tests-sdr-test0.yml
@@ -6,6 +6,10 @@ parameters:
 - name: uhdArtifactSource
   type: string
   default: current
+- name: uhdFpgaArtifactSource
+  type: string
+- name: fpga_imgs_source
+  type: string
 
 jobs:
 - template: templates/job-uhd-x4xx-hardware-tests.yml
@@ -17,6 +21,8 @@ jobs:
     runDevTest: true
     runSystemImageTest: true
     uhdArtifactSource: ${{ parameters.uhdArtifactSource }}
+    uhdFpgaArtifactSource: ${{ parameters.uhdFpgaArtifactSource }}
+    fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
     xilinxLocation: /opt/Xilinx/SDK/2019.1
     dutMatrix:
       sdr-test0-x410-0:
@@ -26,4 +32,5 @@ jobs:
         dutFPGA: 'X4_200'
         dutEmbeddedImagesArtifact: 'x4xx-images'
         uartSerial: '2516351FE64E'
+        pytestDUT: 'x410'
         pipelineAgent: sdr-test0
diff --git a/.ci/templates/tests/job-uhd-x440-hardware-tests-pebbles.yml b/.ci/templates/tests/job-uhd-x440-hardware-tests-pebbles.yml
index 326178e46..18c87ef19 100644
--- a/.ci/templates/tests/job-uhd-x440-hardware-tests-pebbles.yml
+++ b/.ci/templates/tests/job-uhd-x440-hardware-tests-pebbles.yml
@@ -6,6 +6,10 @@ parameters:
 - name: uhdArtifactSource
   type: string
   default: current
+- name: uhdFpgaArtifactSource
+  type: string
+- name: fpga_imgs_source
+  type: string
 - name: extra_rf_test_args
   type: string
   default: ''
@@ -22,6 +26,8 @@ jobs:
     runDevTest: false
     runSystemImageTest: false
     uhdArtifactSource: ${{ parameters.uhdArtifactSource }}
+    uhdFpgaArtifactSource: ${{ parameters.uhdFpgaArtifactSource }}
+    fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
     xilinxLocation: /opt/Xilinx/Vivado/2019.1
     extra_rf_test_args: '${{ parameters.extra_rf_test_args }}'
     testLength: '${{ parameters.testLength }}'
diff --git a/.ci/templates/tests/job-uhd-x440-hardware-tests-saison.yml b/.ci/templates/tests/job-uhd-x440-hardware-tests-saison.yml
index 97ae19017..543b26a71 100644
--- a/.ci/templates/tests/job-uhd-x440-hardware-tests-saison.yml
+++ b/.ci/templates/tests/job-uhd-x440-hardware-tests-saison.yml
@@ -6,6 +6,10 @@ parameters:
 - name: uhdArtifactSource
   type: string
   default: current
+- name: uhdFpgaArtifactSource
+  type: string
+- name: fpga_imgs_source
+  type: string
 - name: extra_rf_test_args
   type: string
   default: ''
@@ -22,6 +26,8 @@ jobs:
     runDevTest: false
     runSystemImageTest: false
     uhdArtifactSource: ${{ parameters.uhdArtifactSource }}
+    uhdFpgaArtifactSource: ${{ parameters.uhdFpgaArtifactSource }}
+    fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
     xilinxLocation: /opt/Xilinx/Vivado/2019.1
     extra_rf_test_args: '${{ parameters.extra_rf_test_args }}'
     testLength: '${{ parameters.testLength }}'
diff --git a/.ci/templates/tests/job-uhd-x440-hardware-tests-sdr-test0.yml b/.ci/templates/tests/job-uhd-x440-hardware-tests-sdr-test0.yml
index 80c7187bc..8e83c9000 100644
--- a/.ci/templates/tests/job-uhd-x440-hardware-tests-sdr-test0.yml
+++ b/.ci/templates/tests/job-uhd-x440-hardware-tests-sdr-test0.yml
@@ -6,6 +6,10 @@ parameters:
 - name: uhdArtifactSource
   type: string
   default: current
+- name: uhdFpgaArtifactSource
+  type: string
+- name: fpga_imgs_source
+  type: string
 
 jobs:
 - template: templates/job-uhd-x4xx-hardware-tests.yml
@@ -17,6 +21,8 @@ jobs:
     runDevTest: true
     runSystemImageTest: true
     uhdArtifactSource: ${{ parameters.uhdArtifactSource }}
+    uhdFpgaArtifactSource: ${{ parameters.uhdFpgaArtifactSource }}
+    fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
     xilinxLocation: /opt/Xilinx/SDK/2019.1
     dutMatrix:
       sdr-test0-x440-0:
@@ -27,4 +33,5 @@ jobs:
         dutFPGA: 'X4_400'
         dutEmbeddedImagesArtifact: 'x4xx-images'
         uartSerial: '25163525D2B3'
+        pytestDUT: 'x440'
         pipelineAgent: sdr-test0
diff --git a/.ci/templates/tests/templates/job-uhd-x4xx-hardware-tests.yml b/.ci/templates/tests/templates/job-uhd-x4xx-hardware-tests.yml
index a55ede196..4ac4fbf65 100644
--- a/.ci/templates/tests/templates/job-uhd-x4xx-hardware-tests.yml
+++ b/.ci/templates/tests/templates/job-uhd-x4xx-hardware-tests.yml
@@ -25,6 +25,10 @@ parameters:
 - name: uhdArtifactSource
   type: string
   default: current
+- name: uhdFpgaArtifactSource
+  type: string
+- name: fpga_imgs_source
+  type: string
 - name: xilinxLocation
   type: string
 - name: extra_rf_test_args
@@ -65,15 +69,34 @@ jobs:
     displayName: Set uhddev pipeline artifact location
 
   - script: |
+      if [ "${{ parameters.uhdFpgaArtifactSource }}" = "current" ]; then
+        echo '##vso[task.setvariable variable=uhd_fpga_artifact_directory]'$(Agent.BuildDirectory)
+      else
+        echo '##vso[task.setvariable variable=uhd_fpga_artifact_directory]'$(Agent.BuildDirectory)/${{ parameters.uhdFpgaArtifactSource }}
+      fi
+    displayName: Set uhddev FPGA pipeline artifact location
+
+  - script: |
       rm -rf $(uhd_artifact_directory)/$(dutEmbeddedImagesArtifact)
       rm -rf $(uhd_artifact_directory)/uhddev-${{ parameters.testOS }}-${{ parameters.toolset }}
       rm -rf $(uhd_artifact_directory)/gnuradio-${{ parameters.testOS }}-${{ parameters.toolset }}
+      if [ ! -z "${{ parameters.uhdFpgaArtifactSource }}" ]; then
+        rm -rf $(Agent.BuildDirectory)/${{ parameters.uhdFpgaArtifactSource }}
+      fi
     displayName: Cleanup from prior run
 
   - download: ${{ parameters.uhdArtifactSource }}
     artifact: $(dutEmbeddedImagesArtifact)
     displayName: Download $(dutEmbeddedImagesArtifact)
 
+  - download: ${{ parameters.uhdFpgaArtifactSource }}
+    patterns: |
+      usrp_$(pytestDUT)_fpga_$(dutFPGA).bit
+      usrp_$(pytestDUT)_fpga_$(dutFPGA).dts
+      usrp_$(pytestDUT)_fpga_$(dutFPGA).rpt
+    displayName: Download FPGA pipeline artifacts
+    condition: and(succeeded(), eq('${{ parameters.fpga_imgs_source }}', 'FPGA Pipeline'))
+
   - task: ExtractFiles@1
     inputs:
       archiveFilePatterns: $(uhd_artifact_directory)/$(dutEmbeddedImagesArtifact)/u-boot-jtag-files.zip
@@ -153,6 +176,14 @@ jobs:
 
   - script: |
         ssh-keygen -f ~/.ssh/known_hosts -R $USRP_EMB_TARGET_IP
+        scp -o StrictHostKeyChecking=no $(uhd_fpga_artifact_directory)/*/usrp_$(pytestDUT)_* root@$USRP_EMB_TARGET_IP:/usr/share/uhd/images/
+        ssh -o StrictHostKeyChecking=no -tt root@$USRP_EMB_TARGET_IP "md5sum /usr/share/uhd/images/usrp_$(pytestDUT)_fpga_$(dutFPGA).bit > /usr/share/uhd/images/usrp_$(pytestDUT)_fpga_$(dutFPGA).bit.md5"
+        ssh -o StrictHostKeyChecking=no -tt root@$USRP_EMB_TARGET_IP "md5sum /usr/share/uhd/images/usrp_$(pytestDUT)_fpga_$(dutFPGA).dts > /usr/share/uhd/images/usrp_$(pytestDUT)_fpga_$(dutFPGA).dts.md5"
+    displayName: Copy FPGA pipeline images to device
+    condition: and(succeeded(), eq('${{ parameters.fpga_imgs_source }}', 'FPGA Pipeline'))
+
+  - script: |
+        ssh-keygen -f ~/.ssh/known_hosts -R $USRP_EMB_TARGET_IP
         ssh -o StrictHostKeyChecking=no -tt root@$USRP_EMB_TARGET_IP "uhd_image_loader --args addr=localhost,type=$(dutType),fpga=$(dutFPGA)"
         EXITCODE=$?
         sleep 60
@@ -205,6 +236,13 @@ jobs:
     continueOnError: true
 
   - script: |
+      export UHD_INSTALL_PATH=$(uhd_artifact_directory)/uhddev-${{ parameters.testOS }}-${{ parameters.toolset }}/uhddev/build-installed
+      export PATH=$UHD_INSTALL_PATH/bin:$PATH
+      if [ -d "$UHD_INSTALL_PATH/lib64" ]; then
+        export LD_LIBRARY_PATH=$UHD_INSTALL_PATH/lib64:$LD_LIBRARY_PATH
+      else
+        export LD_LIBRARY_PATH=$UHD_INSTALL_PATH/lib:$LD_LIBRARY_PATH
+      fi
       mkdir -p $(Common.TestResultsDirectory)/devtest
       cd $(Common.TestResultsDirectory)/devtest
       if [ -z "$(master_clock_rate)" ]; then
@@ -213,6 +251,7 @@ jobs:
         args="addr=$USRP_EMB_TARGET_IP,type=$(dutType),master_clock_rate=$(master_clock_rate)"
       fi
       echo $args
+      uhd_usrp_probe --args $args
       python3 $(Build.SourcesDirectory)/uhddev/host/tests/devtest/run_testsuite.py \
         --src-dir $(Build.SourcesDirectory)/uhddev/host/tests/devtest \
         --devtest-pattern $(devtestPattern) --args $args \
@@ -267,6 +306,7 @@ jobs:
         sleep ${{ parameters.warmUpAfterBoot }}
       fi
       uhd_find_devices --args type=$(dutType)
+      uhd_usrp_probe --args addr=$USRP_EMB_TARGET_IP,type=$(dutType)
       python3 ../automated_main.py --ats_config $(pytestAtsConfig) --dut $(pytestDUT) --results_path '$(Common.TestResultsDirectory)/pytest/host' --test_length ${{ parameters.testLength }} ${{ parameters.extra_rf_test_args }}
     displayName: Run pytest on host
     continueOnError: true
diff --git a/.ci/uhd-hardware-test-dev.yml b/.ci/uhd-hardware-test-dev.yml
index eaa719b81..deba1a674 100644
--- a/.ci/uhd-hardware-test-dev.yml
+++ b/.ci/uhd-hardware-test-dev.yml
@@ -95,6 +95,8 @@ stages:
     parameters:
       testOS: ubuntu1804
       uhdArtifactSource: uhd_mono_pipeline
+      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
 
 - stage: test_uhd_x440_embedded_stage
   displayName: Test X440 Embedded UHD
@@ -105,6 +107,8 @@ stages:
     parameters:
       testOS: ubuntu1804
       uhdArtifactSource: uhd_mono_pipeline
+      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
 
 - stage: test_streaming_stage
   displayName: Test UHD Streaming
@@ -166,6 +170,8 @@ stages:
     parameters:
       testOS: ubuntu1804
       uhdArtifactSource: uhd_mono_pipeline
+      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       extra_rf_test_args: ${{ parameters.extra_rf_test_args }}
       testLength: ${{ parameters.testLength }}
 
@@ -179,6 +185,8 @@ stages:
     parameters:
       testOS: ubuntu1804
       uhdArtifactSource: uhd_mono_pipeline
+      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       extra_rf_test_args: ${{ parameters.extra_rf_test_args }}
       testLength: ${{ parameters.testLength }}
 
@@ -191,6 +199,8 @@ stages:
     parameters:
       testOS: ubuntu2204
       uhdArtifactSource: uhd_mono_pipeline
+      uhdFpgaArtifactSource: uhd_fpga_pipeline
+      fpga_imgs_source: ${{ parameters.fpga_imgs_source }}
       ${{ if contains(parameters['extra_rf_test_args'],  'test_selector') }}:
         extra_rf_test_args: ${{ parameters.extra_rf_test_args }}
       ${{ else }}: