fpga: Add option to build IP only

5 files changed, 25 insertions, 10 deletions

diff --git a/fpga/usrp3/top/e31x/Makefile b/fpga/usrp3/top/e31x/Makefile
index 83257a353..ee2966173 100644
--- a/fpga/usrp3/top/e31x/Makefile
+++ b/fpga/usrp3/top/e31x/Makefile
@@ -23,10 +23,12 @@ DEFS += BUILD_SEED=$(BUILD_SEED)
 
 # Set build option (check RTL, run synthesis, or do a full build)
 ifndef TARGET
-	ifdef CHECK
+	ifeq ($(CHECK), 1)
 		TARGET = rtl
-	else ifdef SYNTH
+	else ifeq ($(SYNTH), 1)
 		TARGET = synth
+	else ifeq ($(IP_ONLY), 1)
+		TARGET = viv_ip
 	else
 		TARGET = bin
 	endif
@@ -114,6 +116,7 @@ help:           ##Show this help message.
 ##GUI=1          Launch the build in the Vivado GUI.
 ##PROJECT=1      Save Vivado project file, otherwise it's created in memory.
 ##CHECK=1        Launch the syntax checker instead of building a bitfile.
+##IP_ONLY=1      Launch the build but stop after IP generation.
 ##SYNTH=1        Launch the build but stop after synthesis.
 ##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
 ##TOP=<module>   Specify a top module for syntax checking. (Default is the bitfile top)
diff --git a/fpga/usrp3/top/e320/Makefile b/fpga/usrp3/top/e320/Makefile
index cf22938ad..f12045638 100644
--- a/fpga/usrp3/top/e320/Makefile
+++ b/fpga/usrp3/top/e320/Makefile
@@ -26,10 +26,12 @@ AA_DEFS=SFP_AURORA=1 BUILD_AURORA=1 $(OPTIONS) BUILD_SEED=$(BUILD_SEED)
 
 # Set build option (check RTL, run synthesis, or do a full build)
 ifndef TARGET
-	ifdef CHECK
+	ifeq ($(CHECK), 1)
 		TARGET = rtl
-	else ifdef SYNTH
+	else ifeq ($(SYNTH), 1)
 		TARGET = synth
+	else ifeq ($(IP_ONLY), 1)
+		TARGET = viv_ip
 	else
 		TARGET = bin
 	endif
@@ -106,6 +108,7 @@ help:     ##Show this help message.
 ##GUI=1          Launch the build in the Vivado GUI.
 ##PROJECT=1      Save Vivado project file, otherwise it's created in memory.
 ##CHECK=1        Launch the syntax checker instead of building a bitfile.
+##IP_ONLY=1      Launch the build but stop after IP generation.
 ##SYNTH=1        Launch the build but stop after synthesis.
 ##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
 ##TOP=<module>   Specify a top module for syntax checking. (Default is the bitfile top)
diff --git a/fpga/usrp3/top/n3xx/Makefile b/fpga/usrp3/top/n3xx/Makefile
index 62b85c3c1..5525af8f0 100644
--- a/fpga/usrp3/top/n3xx/Makefile
+++ b/fpga/usrp3/top/n3xx/Makefile
@@ -49,10 +49,12 @@ N320AA_DEFAULTS:=DEFAULT_RFNOC_IMAGE_CORE_FILE=$(abspath n320_bist_image_core.v)
 
 # Set build option (check RTL, run synthesis, or do a full build)
 ifndef TARGET
-	ifdef CHECK
+	ifeq ($(CHECK), 1)
 		TARGET = rtl
-	else ifdef SYNTH
+	else ifeq ($(SYNTH), 1)
 		TARGET = synth
+	else ifeq ($(IP_ONLY), 1)
+		TARGET = viv_ip
 	else
 		TARGET = bin
 	endif
@@ -209,6 +211,7 @@ help:     ##Show this help message.
 ##GUI=1          Launch the build in the Vivado GUI.
 ##PROJECT=1      Save Vivado project file, otherwise it's created in memory.
 ##CHECK=1        Launch the syntax checker instead of building a bitfile.
+##IP_ONLY=1      Launch the build but stop after IP generation.
 ##SYNTH=1        Launch the build but stop after synthesis.
 ##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
 ##TOP=<module>   Specify a top module for syntax checking. (Default is the bitfile top)
diff --git a/fpga/usrp3/top/x300/Makefile b/fpga/usrp3/top/x300/Makefile
index 3d974a84e..82e1d77ee 100644
--- a/fpga/usrp3/top/x300/Makefile
+++ b/fpga/usrp3/top/x300/Makefile
@@ -35,10 +35,12 @@ XA_DEFS=BUILD_10G=1 BUILD_AURORA=1 SFP0_10GBE=1 SFP1_AURORA=1 $(OPTIONS) BUILD_S
 
 # Set build option (check RTL, run synthesis, or do a full build)
 ifndef TARGET
-	ifdef CHECK
+	ifeq ($(CHECK), 1)
 		TARGET = rtl
-	else ifdef SYNTH
+	else ifeq ($(SYNTH), 1)
 		TARGET = synth
+	else ifeq ($(IP_ONLY), 1)
+		TARGET = viv_ip
 	else
 		TARGET = bin
 	endif
@@ -155,6 +157,7 @@ help:     ##Show this help message.
 ##GUI=1          Launch the build in the Vivado GUI.
 ##PROJECT=1      Save Vivado project file, otherwise it's created in memory.
 ##CHECK=1        Launch the syntax checker instead of building a bitfile.
+##IP_ONLY=1      Launch the build but stop after IP generation.
 ##SYNTH=1        Launch the build but stop after synthesis.
 ##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
 ##TOP=<module>   Specify a top module for syntax checking. (Default is the bitfile top)
diff --git a/fpga/usrp3/top/x400/Makefile b/fpga/usrp3/top/x400/Makefile
index 1bf0d3fcd..81ea87b02 100644
--- a/fpga/usrp3/top/x400/Makefile
+++ b/fpga/usrp3/top/x400/Makefile
@@ -99,10 +99,12 @@ X440_1600_D_DEFAULTS  := DEFAULT_RFNOC_IMAGE_CORE_FILE=x440_1600_d_rfnoc_image_c
 
 # Option to stop after RTL elaboration. Use this flag as a synthesis check.
 ifndef TARGET
-	ifdef CHECK
+	ifeq ($(CHECK), 1)
 		TARGET = rtl
-	else ifdef SYNTH
+	else ifeq ($(SYNTH), 1)
 		TARGET = synth
+	else ifeq ($(IP_ONLY), 1)
+		TARGET = viv_ip
 	else
 		TARGET = bin
 	endif
@@ -333,6 +335,7 @@ help:         ##Show this help message.
 ##GUI=1          Launch the build in the Vivado GUI.
 ##PROJECT=1      Save Vivado project file, otherwise it's created in memory.
 ##CHECK=1        Launch the syntax checker instead of building a bitfile.
+##IP_ONLY=1      Launch the build but stop after IP generation.
 ##SYNTH=1        Launch the build but stop after synthesis.
 ##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
 ##TOP=<module>   Specify a top module for syntax checking. (Default is the bitfile top)