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| author |   Wade Fife <wade.fife@ettus.com> | 2024-03-06 11:27:18 -0600 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2024-03-15 20:05:39 -0500 |
| commit | 8f9beccebe54a21d4993f8298c184426671624b0 (patch) | |
| tree | 42e02f369db9460cfb31bd580f20fcf43908a00e /fpga/usrp3/tools/make/viv_preamble.mak | |
| parent | fpga: ci: Update n3xx BIST image cores (diff) | |
| download | uhd-8f9beccebe54a21d4993f8298c184426671624b0.tar.xz uhd-8f9beccebe54a21d4993f8298c184426671624b0.zip | |
fpga: tools: Add option to save Vivado project
Diffstat (limited to 'fpga/usrp3/tools/make/viv_preamble.mak')
| -rw-r--r-- | fpga/usrp3/tools/make/viv_preamble.mak | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/fpga/usrp3/tools/make/viv_preamble.mak b/fpga/usrp3/tools/make/viv_preamble.mak index 8469c0581..ea2bd92fd 100644 --- a/fpga/usrp3/tools/make/viv_preamble.mak +++ b/fpga/usrp3/tools/make/viv_preamble.mak @@ -53,6 +53,15 @@ VIVADO_MODE=batch endif # ------------------------------------------------------------------- +# Project mode switch. Calling with PROJECT:=1 will use Vivado project file +# ------------------------------------------------------------------- +ifeq ($(PROJECT),1) +VIVADO_PROJECT=1 +else +VIVADO_PROJECT=0 +endif + +# ------------------------------------------------------------------- # Toolchain dependency target # ------------------------------------------------------------------- .check_tool: |