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authorWade Fife <wade.fife@ettus.com>2024-03-06 11:28:05 -0600
committerWade Fife <wade.fife@ettus.com>2024-03-15 20:05:39 -0500
commit2e0db35eaf69947c344f67c9f38132e33f88a141 (patch)
tree77b6a1fb0cffbe312ee0ec1758e2999a06cbae44 /host/python/uhd/imgbuilder/image_builder.py
parentfpga: tools: Add option to save Vivado project (diff)
downloaduhd-2e0db35eaf69947c344f67c9f38132e33f88a141.tar.xz
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fpga: Add Vivado project option to USRP FPGA builds
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