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| author |   Wade Fife <wade.fife@ettus.com> | 2024-03-06 11:28:05 -0600 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2024-03-15 20:05:39 -0500 |
| commit | 2e0db35eaf69947c344f67c9f38132e33f88a141 (patch) | |
| tree | 77b6a1fb0cffbe312ee0ec1758e2999a06cbae44 | |
| parent | fpga: tools: Add option to save Vivado project (diff) | |
| download | uhd-2e0db35eaf69947c344f67c9f38132e33f88a141.tar.xz uhd-2e0db35eaf69947c344f67c9f38132e33f88a141.zip | |
fpga: Add Vivado project option to USRP FPGA builds
| -rw-r--r-- | fpga/usrp3/top/e31x/Makefile | 1 | ||||
| -rw-r--r-- | fpga/usrp3/top/e320/Makefile | 1 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/Makefile | 1 | ||||
| -rw-r--r-- | fpga/usrp3/top/x300/Makefile | 1 | ||||
| -rw-r--r-- | fpga/usrp3/top/x400/Makefile | 1 |
5 files changed, 5 insertions, 0 deletions
diff --git a/fpga/usrp3/top/e31x/Makefile b/fpga/usrp3/top/e31x/Makefile index 8c0e32b56..83257a353 100644 --- a/fpga/usrp3/top/e31x/Makefile +++ b/fpga/usrp3/top/e31x/Makefile @@ -112,6 +112,7 @@ help: ##Show this help message. ##DRAM=1 Include DDR3 SDRAM memory controller IP in the FPGA build. ## Note: The RFNoC image core must also be configured to use DRAM. ##GUI=1 Launch the build in the Vivado GUI. +##PROJECT=1 Save Vivado project file, otherwise it's created in memory. ##CHECK=1 Launch the syntax checker instead of building a bitfile. ##SYNTH=1 Launch the build but stop after synthesis. ##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0) diff --git a/fpga/usrp3/top/e320/Makefile b/fpga/usrp3/top/e320/Makefile index e2e6e8a79..cf22938ad 100644 --- a/fpga/usrp3/top/e320/Makefile +++ b/fpga/usrp3/top/e320/Makefile @@ -104,6 +104,7 @@ help: ##Show this help message. ##Supported Options ##----------------- ##GUI=1 Launch the build in the Vivado GUI. +##PROJECT=1 Save Vivado project file, otherwise it's created in memory. ##CHECK=1 Launch the syntax checker instead of building a bitfile. ##SYNTH=1 Launch the build but stop after synthesis. ##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0) diff --git a/fpga/usrp3/top/n3xx/Makefile b/fpga/usrp3/top/n3xx/Makefile index 5abafb3cd..62b85c3c1 100644 --- a/fpga/usrp3/top/n3xx/Makefile +++ b/fpga/usrp3/top/n3xx/Makefile @@ -207,6 +207,7 @@ help: ##Show this help message. ##Supported Options ##----------------- ##GUI=1 Launch the build in the Vivado GUI. +##PROJECT=1 Save Vivado project file, otherwise it's created in memory. ##CHECK=1 Launch the syntax checker instead of building a bitfile. ##SYNTH=1 Launch the build but stop after synthesis. ##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0) diff --git a/fpga/usrp3/top/x300/Makefile b/fpga/usrp3/top/x300/Makefile index 5c08fc1e1..3d974a84e 100644 --- a/fpga/usrp3/top/x300/Makefile +++ b/fpga/usrp3/top/x300/Makefile @@ -153,6 +153,7 @@ help: ##Show this help message. ##Supported Options ##----------------- ##GUI=1 Launch the build in the Vivado GUI. +##PROJECT=1 Save Vivado project file, otherwise it's created in memory. ##CHECK=1 Launch the syntax checker instead of building a bitfile. ##SYNTH=1 Launch the build but stop after synthesis. ##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0) diff --git a/fpga/usrp3/top/x400/Makefile b/fpga/usrp3/top/x400/Makefile index a42c7b05d..1bf0d3fcd 100644 --- a/fpga/usrp3/top/x400/Makefile +++ b/fpga/usrp3/top/x400/Makefile @@ -331,6 +331,7 @@ help: ##Show this help message. ##INCR_BUILD=0 Use incremental Vivado build to speed up consecutive runs ##DRAM=0 Exclude DDR4 memory controller IP from the FPGA build. ##GUI=1 Launch the build in the Vivado GUI. +##PROJECT=1 Save Vivado project file, otherwise it's created in memory. ##CHECK=1 Launch the syntax checker instead of building a bitfile. ##SYNTH=1 Launch the build but stop after synthesis. ##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0) |