diff options
Diffstat (limited to 'fpga/usrp3/tools/make')
| -rw-r--r-- | fpga/usrp3/tools/make/viv_design_builder.mak | 1 | ||||
| -rw-r--r-- | fpga/usrp3/tools/make/viv_preamble.mak | 9 |
2 files changed, 10 insertions, 0 deletions
diff --git a/fpga/usrp3/tools/make/viv_design_builder.mak b/fpga/usrp3/tools/make/viv_design_builder.mak index 78e49da06..cd2f0e332 100644 --- a/fpga/usrp3/tools/make/viv_design_builder.mak +++ b/fpga/usrp3/tools/make/viv_design_builder.mak @@ -25,6 +25,7 @@ BUILD_VIVADO_DESIGN = \ export VIV_TOP_MODULE=$(2); \ export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \ export VIV_MODE=$(VIVADO_MODE); \ + export VIV_SAVE=$(VIVADO_SAVE); \ export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \ export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \ export VIV_INCR_BUILD=$(INCR_BUILD); \ diff --git a/fpga/usrp3/tools/make/viv_preamble.mak b/fpga/usrp3/tools/make/viv_preamble.mak index 8469c0581..ea2bd92fd 100644 --- a/fpga/usrp3/tools/make/viv_preamble.mak +++ b/fpga/usrp3/tools/make/viv_preamble.mak @@ -53,6 +53,15 @@ VIVADO_MODE=batch endif # ------------------------------------------------------------------- +# Project mode switch. Calling with PROJECT:=1 will use Vivado project file +# ------------------------------------------------------------------- +ifeq ($(PROJECT),1) +VIVADO_PROJECT=1 +else +VIVADO_PROJECT=0 +endif + +# ------------------------------------------------------------------- # Toolchain dependency target # ------------------------------------------------------------------- .check_tool: |