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Diffstat (limited to 'fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.yml')
| -rw-r--r-- | fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.yml | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.yml b/fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.yml new file mode 100644 index 000000000..bb579cffb --- /dev/null +++ b/fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.yml @@ -0,0 +1,93 @@ +# General parameters +# ----------------------------------------- +schema: rfnoc_imagebuilder_args # Identifier for the schema used to validate this file +copyright: >- # Copyright information used in file headers + Copyright 2023 Ettus Research, a National Instruments Brand +license: >- # License information used in file headers + SPDX-License-Identifier: LGPL-3.0-or-later +version: '1.0' # File version +chdr_width: 64 # Bit width of the CHDR bus for this image +device: 'n300' +image_core_name: 'n300_bist' # Name to use for the RFNoC Image Core files +default_target: 'N300_AA' + +# A list of all stream endpoints in design +# ---------------------------------------- +stream_endpoints: + ep0: # Stream endpoint name + ctrl: True # Endpoint passes control traffic + data: True # Endpoint passes data traffic + buff_size: 16384 # Ingress buffer size for data + ep1: + ctrl: False + data: True + buff_size: 16384 + # We call the next endpoints 4 and 5 to keep them consistent with the + # N310 version of this file + ep4: + ctrl: False + data: True + buff_size: 16384 + ep5: + ctrl: False + data: True + buff_size: 16384 + +# A list of all NoC blocks in design +# ---------------------------------- +noc_blocks: + radio0: + block_desc: 'radio.yml' + parameters: + NUM_PORTS: 2 + fifo0: + block_desc: 'axi_ram_fifo.yml' + parameters: + # These parameters match the memory interface on the N3XX + NUM_PORTS: 4 + MEM_DATA_W: 64 + MEM_ADDR_W: 31 + # Create two non-overlapping 32 MB buffers by default + FIFO_ADDR_BASE: "{31'h06000000, 31'h04000000, 31'h02000000, 31'h00000000}" + FIFO_ADDR_MASK: "{31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF, 31'h01FFFFFF}" + MEM_CLK_RATE: "303819444" # 166.666666 MHz * 21.875 / 4 / 3 = 303.819444 MHz + +# A list of all static connections in design +# ------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect +# - srcport = Port on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Port on the destination block to connect +connections: + # RF 0 TX + - { srcblk: ep0, srcport: out0, dstblk: radio0, dstport: in_0 } + # RF 0 RX + - { srcblk: radio0, srcport: out_0, dstblk: ep0, dstport: in0 } + # RF 1 TX + - { srcblk: ep1, srcport: out0, dstblk: radio0, dstport: in_1 } + # RF 1 RX + - { srcblk: radio0, srcport: out_1, dstblk: ep1, dstport: in0 } + # + # DRAM FIFO Connections + - { srcblk: ep4, srcport: out0, dstblk: fifo0, dstport: in_0 } + - { srcblk: fifo0, srcport: out_0, dstblk: ep4, dstport: in0 } + - { srcblk: ep5, srcport: out0, dstblk: fifo0, dstport: in_1 } + - { srcblk: fifo0, srcport: out_1, dstblk: ep5, dstport: in0 } + # + # BSP Connections + - { srcblk: radio0, srcport: ctrlport, dstblk: _device_, dstport: ctrlport_radio0 } + - { srcblk: fifo0, srcport: axi_ram, dstblk: _device_, dstport: dram } + - { srcblk: _device_, srcport: radio0, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: time, dstblk: radio0, dstport: time } + +# A list of all clock domain connections in design +# ------------------------------------------------ +# Format: A list of connection maps (list of key-value pairs) with the following keys +# - srcblk = Source block to connect (Always "_device"_) +# - srcport = Clock domain on the source block to connect +# - dstblk = Destination block to connect +# - dstport = Clock domain on the destination block to connect +clk_domains: + - { srcblk: _device_, srcport: radio, dstblk: radio0, dstport: radio } + - { srcblk: _device_, srcport: dram, dstblk: fifo0, dstport: mem } |