diff options
| -rw-r--r-- | fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.v (renamed from fpga/usrp3/top/n3xx/n300_bist_image_core.v) | 2 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.vh (renamed from fpga/usrp3/top/n3xx/n300_bist_image_core.vh) | 2 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.yml (renamed from fpga/usrp3/top/n3xx/n300_bist_image_core.yml) | 1 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n310_bist_rfnoc_image_core.v (renamed from fpga/usrp3/top/n3xx/n310_bist_image_core.v) | 2 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n310_bist_rfnoc_image_core.vh (renamed from fpga/usrp3/top/n3xx/n310_bist_image_core.vh) | 2 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n310_bist_rfnoc_image_core.yml (renamed from fpga/usrp3/top/n3xx/n310_bist_image_core.yml) | 1 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n320_bist_rfnoc_image_core.v (renamed from fpga/usrp3/top/n3xx/n320_bist_image_core.v) | 2 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n320_bist_rfnoc_image_core.vh (renamed from fpga/usrp3/top/n3xx/n320_bist_image_core.vh) | 2 | ||||
| -rw-r--r-- | fpga/usrp3/top/n3xx/n320_bist_rfnoc_image_core.yml (renamed from fpga/usrp3/top/n3xx/n320_bist_image_core.yml) | 1 |
9 files changed, 9 insertions, 6 deletions
diff --git a/fpga/usrp3/top/n3xx/n300_bist_image_core.v b/fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.v index b7ef8cae7..ebdde059a 100644 --- a/fpga/usrp3/top/n3xx/n300_bist_image_core.v +++ b/fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.v @@ -13,7 +13,7 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// Source: n300_bist_image_core.yml +// Source: n300_bist_rfnoc_image_core.yml // `default_nettype none diff --git a/fpga/usrp3/top/n3xx/n300_bist_image_core.vh b/fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.vh index d0061b1e7..68cb91ce7 100644 --- a/fpga/usrp3/top/n3xx/n300_bist_image_core.vh +++ b/fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.vh @@ -12,7 +12,7 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// Source: n300_bist_image_core.yml +// Source: n300_bist_rfnoc_image_core.yml // `define CHDR_WIDTH 64 diff --git a/fpga/usrp3/top/n3xx/n300_bist_image_core.yml b/fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.yml index 7d75c1ac0..bb579cffb 100644 --- a/fpga/usrp3/top/n3xx/n300_bist_image_core.yml +++ b/fpga/usrp3/top/n3xx/n300_bist_rfnoc_image_core.yml @@ -8,6 +8,7 @@ license: >- # License information used in file heade version: '1.0' # File version chdr_width: 64 # Bit width of the CHDR bus for this image device: 'n300' +image_core_name: 'n300_bist' # Name to use for the RFNoC Image Core files default_target: 'N300_AA' # A list of all stream endpoints in design diff --git a/fpga/usrp3/top/n3xx/n310_bist_image_core.v b/fpga/usrp3/top/n3xx/n310_bist_rfnoc_image_core.v index d85c811f1..56c350b38 100644 --- a/fpga/usrp3/top/n3xx/n310_bist_image_core.v +++ b/fpga/usrp3/top/n3xx/n310_bist_rfnoc_image_core.v @@ -13,7 +13,7 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// Source: n310_bist_image_core.yml +// Source: n310_bist_rfnoc_image_core.yml // `default_nettype none diff --git a/fpga/usrp3/top/n3xx/n310_bist_image_core.vh b/fpga/usrp3/top/n3xx/n310_bist_rfnoc_image_core.vh index 9efec698d..09fdf4689 100644 --- a/fpga/usrp3/top/n3xx/n310_bist_image_core.vh +++ b/fpga/usrp3/top/n3xx/n310_bist_rfnoc_image_core.vh @@ -12,7 +12,7 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// Source: n310_bist_image_core.yml +// Source: n310_bist_rfnoc_image_core.yml // `define CHDR_WIDTH 64 diff --git a/fpga/usrp3/top/n3xx/n310_bist_image_core.yml b/fpga/usrp3/top/n3xx/n310_bist_rfnoc_image_core.yml index ec7e66534..dda784d08 100644 --- a/fpga/usrp3/top/n3xx/n310_bist_image_core.yml +++ b/fpga/usrp3/top/n3xx/n310_bist_rfnoc_image_core.yml @@ -8,6 +8,7 @@ license: >- # License information used in file heade version: '1.0' # File version chdr_width: 64 # Bit width of the CHDR bus for this block device: 'n310' +image_core_name: 'n310_bist' # Name to use for the RFNoC Image Core files default_target: 'N310_AA' # A list of all stream endpoints in design diff --git a/fpga/usrp3/top/n3xx/n320_bist_image_core.v b/fpga/usrp3/top/n3xx/n320_bist_rfnoc_image_core.v index 0d42234fc..c059e42ee 100644 --- a/fpga/usrp3/top/n3xx/n320_bist_image_core.v +++ b/fpga/usrp3/top/n3xx/n320_bist_rfnoc_image_core.v @@ -13,7 +13,7 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// Source: n320_bist_image_core.yml +// Source: n320_bist_rfnoc_image_core.yml // `default_nettype none diff --git a/fpga/usrp3/top/n3xx/n320_bist_image_core.vh b/fpga/usrp3/top/n3xx/n320_bist_rfnoc_image_core.vh index 7a85ba48c..8f0a101c4 100644 --- a/fpga/usrp3/top/n3xx/n320_bist_image_core.vh +++ b/fpga/usrp3/top/n3xx/n320_bist_rfnoc_image_core.vh @@ -12,7 +12,7 @@ // This file was automatically generated by the RFNoC image builder tool. // Re-running that tool will overwrite this file! // -// Source: n320_bist_image_core.yml +// Source: n320_bist_rfnoc_image_core.yml // `define CHDR_WIDTH 64 diff --git a/fpga/usrp3/top/n3xx/n320_bist_image_core.yml b/fpga/usrp3/top/n3xx/n320_bist_rfnoc_image_core.yml index 744d8129a..048e8a6b3 100644 --- a/fpga/usrp3/top/n3xx/n320_bist_image_core.yml +++ b/fpga/usrp3/top/n3xx/n320_bist_rfnoc_image_core.yml @@ -8,6 +8,7 @@ license: >- # License information used in file heade version: '1.0' # File version chdr_width: 64 # Bit width of the CHDR bus for this block device: 'n320' +image_core_name: 'n320_bist' # Name to use for the RFNoC Image Core files default_target: 'N320_AA' # A list of all stream endpoints in design |