diff options
| author |   Doug Brown <doug@schmorgal.com> | 2022-06-12 12:29:31 -0700 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2022-09-30 13:34:06 -0700 |
| commit | 30c0368207b1efa3bbcafcdca0b1749a375f86e3 (patch) | |
| tree | 308ec729c7da269aa1ab5fb44c857760c98ce036 /drivers/clk/mmp | |
| parent | clk: mmp: pxa168: fix const-correctness (diff) | |
| download | wireguard-linux-30c0368207b1efa3bbcafcdca0b1749a375f86e3.tar.xz wireguard-linux-30c0368207b1efa3bbcafcdca0b1749a375f86e3.zip | |
clk: mmp: pxa168: fix incorrect parent clocks
The UART, SDHC, LCD, and CCIC peripherals' muxed parent clocks didn't
match the information provided by the PXA168 datasheet:
- The UART clocks can be 58.5 MHz or the UART PLL. Previously, the first
mux option was being calculated as 117 MHz, confirmed on hardware to
be incorrect.
- The SDHC clocks can be 48 MHz, 52 MHz, or 78 MHz. Previously, 48 MHz
and 52 MHz were swapped. 78 MHz wasn't listed as an option.
- The LCD clock can be 624 MHz or 312 Mhz. Previously, it was being
calculated as 312 MHz or 52 MHz.
- The CCIC clock can be 156 MHz or 78 MHz. Previously, it was being
calculated as 312 MHz or 52 MHz.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-7-doug@schmorgal.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mmp')
| -rw-r--r-- | drivers/clk/mmp/clk-of-pxa168.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c index e6ae362fb565..3a1febb53786 100644 --- a/drivers/clk/mmp/clk-of-pxa168.c +++ b/drivers/clk/mmp/clk-of-pxa168.c @@ -130,7 +130,7 @@ static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit) static DEFINE_SPINLOCK(uart0_lock); static DEFINE_SPINLOCK(uart1_lock); static DEFINE_SPINLOCK(uart2_lock); -static const char * const uart_parent_names[] = {"pll1_3_16", "uart_pll"}; +static const char * const uart_parent_names[] = {"pll1_2_3_16", "uart_pll"}; static DEFINE_SPINLOCK(ssp0_lock); static DEFINE_SPINLOCK(ssp1_lock); @@ -192,20 +192,20 @@ static void pxa168_apb_periph_clk_init(struct pxa168_clk_unit *pxa_unit) static DEFINE_SPINLOCK(sdh0_lock); static DEFINE_SPINLOCK(sdh1_lock); -static const char * const sdh_parent_names[] = {"pll1_12", "pll1_13"}; +static const char * const sdh_parent_names[] = {"pll1_13", "pll1_12", "pll1_8"}; static DEFINE_SPINLOCK(usb_lock); static DEFINE_SPINLOCK(disp0_lock); -static const char * const disp_parent_names[] = {"pll1_2", "pll1_12"}; +static const char * const disp_parent_names[] = {"pll1", "pll1_2"}; static DEFINE_SPINLOCK(ccic0_lock); -static const char * const ccic_parent_names[] = {"pll1_2", "pll1_12"}; +static const char * const ccic_parent_names[] = {"pll1_4", "pll1_8"}; static const char * const ccic_phy_parent_names[] = {"pll1_6", "pll1_12"}; static struct mmp_param_mux_clk apmu_mux_clks[] = { - {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock}, - {0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 1, 0, &sdh1_lock}, + {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 2, 0, &sdh0_lock}, + {0, "sdh1_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH1, 6, 2, 0, &sdh1_lock}, {0, "disp0_mux", disp_parent_names, ARRAY_SIZE(disp_parent_names), CLK_SET_RATE_PARENT, APMU_DISP0, 6, 1, 0, &disp0_lock}, {0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 6, 1, 0, &ccic0_lock}, {0, "ccic0_phy_mux", ccic_phy_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0_lock}, |