diff options
| author |   Doug Brown <doug@schmorgal.com> | 2022-06-12 12:29:30 -0700 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2022-09-30 13:34:06 -0700 |
| commit | e2fd64dd472bea0da332da0cc8e8946d2d3294c4 (patch) | |
| tree | 99d35a6890abc9463c8c7ef30a0d205a962b721d /drivers/clk/mmp | |
| parent | clk: mmp: pxa168: add new clocks for peripherals (diff) | |
| download | wireguard-linux-e2fd64dd472bea0da332da0cc8e8946d2d3294c4.tar.xz wireguard-linux-e2fd64dd472bea0da332da0cc8e8946d2d3294c4.zip | |
clk: mmp: pxa168: fix const-correctness
While working on this series of patches, checkpatch recommended that
an extra const should be added to the mux parent arrays.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-6-doug@schmorgal.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mmp')
| -rw-r--r-- | drivers/clk/mmp/clk-of-pxa168.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/clk/mmp/clk-of-pxa168.c b/drivers/clk/mmp/clk-of-pxa168.c index 2526d56a450b..e6ae362fb565 100644 --- a/drivers/clk/mmp/clk-of-pxa168.c +++ b/drivers/clk/mmp/clk-of-pxa168.c @@ -130,17 +130,17 @@ static void pxa168_pll_init(struct pxa168_clk_unit *pxa_unit) static DEFINE_SPINLOCK(uart0_lock); static DEFINE_SPINLOCK(uart1_lock); static DEFINE_SPINLOCK(uart2_lock); -static const char *uart_parent_names[] = {"pll1_3_16", "uart_pll"}; +static const char * const uart_parent_names[] = {"pll1_3_16", "uart_pll"}; static DEFINE_SPINLOCK(ssp0_lock); static DEFINE_SPINLOCK(ssp1_lock); static DEFINE_SPINLOCK(ssp2_lock); static DEFINE_SPINLOCK(ssp3_lock); static DEFINE_SPINLOCK(ssp4_lock); -static const char *ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"}; +static const char * const ssp_parent_names[] = {"pll1_96", "pll1_48", "pll1_24", "pll1_12"}; static DEFINE_SPINLOCK(timer_lock); -static const char *timer_parent_names[] = {"pll1_48", "clk32", "pll1_96", "pll1_192"}; +static const char * const timer_parent_names[] = {"pll1_48", "clk32", "pll1_96", "pll1_192"}; static DEFINE_SPINLOCK(reset_lock); @@ -192,16 +192,16 @@ static void pxa168_apb_periph_clk_init(struct pxa168_clk_unit *pxa_unit) static DEFINE_SPINLOCK(sdh0_lock); static DEFINE_SPINLOCK(sdh1_lock); -static const char *sdh_parent_names[] = {"pll1_12", "pll1_13"}; +static const char * const sdh_parent_names[] = {"pll1_12", "pll1_13"}; static DEFINE_SPINLOCK(usb_lock); static DEFINE_SPINLOCK(disp0_lock); -static const char *disp_parent_names[] = {"pll1_2", "pll1_12"}; +static const char * const disp_parent_names[] = {"pll1_2", "pll1_12"}; static DEFINE_SPINLOCK(ccic0_lock); -static const char *ccic_parent_names[] = {"pll1_2", "pll1_12"}; -static const char *ccic_phy_parent_names[] = {"pll1_6", "pll1_12"}; +static const char * const ccic_parent_names[] = {"pll1_2", "pll1_12"}; +static const char * const ccic_phy_parent_names[] = {"pll1_6", "pll1_12"}; static struct mmp_param_mux_clk apmu_mux_clks[] = { {0, "sdh0_mux", sdh_parent_names, ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT, APMU_SDH0, 6, 1, 0, &sdh0_lock}, |