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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-07-02 20:53:12 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2025-07-02 20:53:12 +0200 |
| commit | 15bf4a46174aa4aff346d17f28821cb9cb6f0034 (patch) | |
| tree | 2ec81890c9d37deff6e7867563a2235af97b04e6 /tools/perf/scripts/python | |
| parent | clk: renesas: r9a09g077: Add RIIC module clocks (diff) | |
| parent | dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock (diff) | |
| download | wireguard-linux-15bf4a46174aa4aff346d17f28821cb9cb6f0034.tar.xz wireguard-linux-15bf4a46174aa4aff346d17f28821cb9cb6f0034.zip | |
Merge tag 'renesas-r9a09g057-dt-binding-defs-tag4' into renesas-clk-for-v6.17
Renesas RZ/V2N and RZ/V2H XSPI Clock DT Binding Definitions
Expanded Serial Peripheral Interface (XSPI) clock DT binding definitions
for the Renesas RZ/V2N (R9A09G056) and RZ/V2H (R9A09G057) SoCs, shared
by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python')
0 files changed, 0 insertions, 0 deletions