aboutsummaryrefslogtreecommitdiffstatshomepage
path: root/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml (follow)
AgeCommit message (Collapse)AuthorFilesLines
2023-10-23dt-bindings: PCI: dwc: Update maxItems of reg and reg-namesYoshihiro Shimoda1-2/+2
Update maxItems of reg and reg-names on both host and endpoint for supporting Renesas R-Car Gen4 PCIe controllers later. Link: https://lore.kernel.org/linux-pci/20231018085631.1121289-10-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org> Reviewed-by: Serge Semin <fancer.lancer@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Manivannan Sadhasivam <mani@kernel.org> Acked-by: Rob Herring <robh@kernel.org>
2022-11-23dt-bindings: PCI: dwc: Add clocks/resets common propertiesSerge Semin1-0/+6
DW PCIe RP/EP reference manuals explicit define all the clocks and reset requirements in [1] and [2]. Seeing the DW PCIe vendor-specific DT-bindings have already started assigning random names to the same set of the clocks and resets lines, let's define a generic names sets and add them to the DW PCIe common DT-schema. Note since there are DW PCI-based vendor-specific DT-bindings with the custom names assigned to the same clocks and resets resources we have no much choice but to add them to the generic DT-schemas in order to have the schemas being applicable for such devices. These names are marked as vendor-specific and should be avoided being used in new bindings in favor of the generic names. [1] Synopsys DesignWare Cores PCI Express Controller Databook - DWC PCIe Root Port, Version 5.40a, March 2019, p.55 - 78. [2] Synopsys DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint, Version 5.40a, March 2019, p.58 - 81. Link: https://lore.kernel.org/r/20221113191301.5526-12-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org>
2022-11-23dt-bindings: PCI: dwc: Add reg/reg-names common propertiesSerge Semin1-7/+75
Even though there is a more-or-less limited set of the CSR spaces can be defined for each DW PCIe controller the generic DT-schema currently doesn't specify much limitations on the reg-space names used for one or another range. In order to prevent the vendor-specific controller schemas further deviation from the generic interface let's fix that by introducing the reg-names definition in the common DW PCIe DT-schemas and preserving the generic "reg" and "reg-names" properties in there. New DW PCIe device DT-bindings are encouraged to use the generic set of the CSR spaces defined in the generic DW PCIe RP/EP DT-bindings, while the already available vendor-specific DT-bindings can still apple the common DT-schemas. Note the number of reg/reg-names items need to be changed in the DW PCIe EP DT-schema since aside with the "dbi" CSRs space these arrays can have "dbi2", "addr_space", "atu", etc ranges. Also note since there are DW PCIe-based vendor-specific DT-bindings with the custom names assigned to the same CSR resources we have no much choice but to add them to the generic DT-schemas in order to have the schemas being applicable for such devices. These names are marked as vendor-specific and should be avoided being used in new bindings in favor of the generic names. Link: https://lore.kernel.org/r/20221113191301.5526-11-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org>
2022-11-23dt-bindings: PCI: dwc: Add interrupts/interrupt-names common propertiesSerge Semin1-0/+52
Currently the 'interrupts' and 'interrupt-names' properties are defined being too generic to really describe any actual IRQ interface. Moreover the DW PCIe End-point devices are left with no IRQ signals. All of that can be fixed by adding the IRQ-related properties to the common DW PCIe DT-schemas in accordance with the hardware reference manual. The DW PCIe common DT-schema will contain the generic properties definitions with just a number of entries per property, while the DW PCIe RP/EP-specific schemas will have the particular number of items and the generic resource names listed. Note since there are DW PCI-based vendor-specific DT-bindings with the custom names assigned to the same IRQ resources we have no much choice but to add them to the generic DT-schemas in order to have the schemas being applicable for such devices. These names are marked as vendor-specific and should be avoided being used in new bindings in favor of the generic names. Link: https://lore.kernel.org/r/20221113191301.5526-10-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org>
2022-11-23dt-bindings: PCI: dwc: Add max-functions EP propertySerge Semin1-0/+4
In accordance with [1] the CX_NFUNC IP-core synthesize parameter is responsible for the number of physical functions to support in the EP mode. Its upper limit is 32. Let's use it to constrain the number of PCIe functions the DW PCIe EP DT-nodes can advertise. [1] Synopsys DesignWare Cores PCI Express Controller Databook - DWC PCIe Endpoint, Version 5.40a, March 2019, p. 887. Link: https://lore.kernel.org/r/20221113191301.5526-9-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org>
2022-11-23dt-bindings: PCI: dwc: Apply generic schema for generic device onlySerge Semin1-6/+10
Having the generic compatible strings constraints with the 'any'+'generic string' semantic implicitly encourages either to add new DW PCIe-based DT-bindings with the generic compatible string attached or just forget about adding new DT-bindings since the corresponding DT-node will be evaluated anyway. Moreover having that semantic implemented in the generic DT-schema causes the DT-validation tool to apply the schema twice: first by implicit compatible-string-based selection and second by means of the 'allOf: [ $ref ]' statement. Let's fix all of that by dropping the compatible property constraints and selecting the generic DT-schema only for the purely generic DW PCIe DT-nodes. The later is required since there is a driver for such devices. (Though there are no such DT-nodes currently defined in the kernel DT sources.) Link: https://lore.kernel.org/r/20221113191301.5526-8-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org>
2022-11-23dt-bindings: PCI: dwc: Add max-link-speed common propertySerge Semin1-0/+2
In accordance with [1] DW PCIe controllers support up to Gen5 link speed. Let's add the max-link-speed property upper bound to 5 then. The DT bindings of the particular devices are expected to setup more strict constraint on that parameter. [1] Synopsys DesignWare Cores PCI Express Controller Databook, Version 5.40a, March 2019, p. 27 Link: https://lore.kernel.org/r/20221113191301.5526-7-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org>
2022-11-23dt-bindings: PCI: dwc: Add phys/phy-names common propertiesSerge Semin1-0/+3
It's normal to have the DW PCIe RP/EP DT-nodes equipped with the explicit PHY phandle references. There can be up to 16 PHYs attach in accordance with the maximum number of supported PCIe lanes. Let's extend the common DW PCIe controller schema with the 'phys' and 'phy-names' properties definition. There two types PHY names are defined: preferred generic names '^pcie[0-9]+$' and non-preferred vendor-specific names '^pcie([0-9]+|-?phy[0-9]*)?$' so to match the names currently supported by the DW PCIe platform drivers ("pcie": meson; "pciephy": qcom, imx6; "pcie-phy": uniphier, rockchip, spear13xx; "pcie": intel-gw; "pcie-phy%d": keystone, dra7xx; "pcie": histb, etc). Link: https://lore.kernel.org/r/20221113191301.5526-6-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org>
2022-11-23dt-bindings: PCI: dwc: Remove bus node from the examplesSerge Semin1-10/+6
It's absolutely redundant seeing by default each node is embedded into its own example-X node with address and size cells set to 1. Link: https://lore.kernel.org/r/20221113191301.5526-5-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org>
2022-11-23dt-bindings: PCI: dwc: Detach common RP/EP DT bindingsSerge Semin1-30/+1
Currently both DW PCIe Root Port and End-point DT bindings are defined as separate schemas. Carefully looking at them, at the hardware reference manuals and seeing there is a generic part of the driver used by the both RP and EP drivers we can greatly simplify the DW PCIe controller bindings by moving some of the properties into the common DT schema. It concerns the PERST GPIO control, number of lanes, number of iATU windows and CDM check properties. They will be defined in the snps,dw-pcie-common.yaml schema which will be referenced in the DW PCIe Root Port and End-point DT bindings in order to evaluate the common for both of these controllers properties. The rest of properties like reg{,-names}, clock{s,-names}, reset{s,-names}, etc will be consolidate there in one of the next commits. Link: https://lore.kernel.org/r/20221113191301.5526-4-Sergey.Semin@baikalelectronics.ru Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org>
2022-05-23dt-bindings: Fix properties without any typeRob Herring1-2/+4
Now that the schema tools can extract type information for all properties (in order to decode dtb files), finding properties missing any type definition is fairly trivial though not yet automated. Fix the various property schemas which are missing a type. Most of these tend to be device specific properties which don't have a vendor prefix. A vendor prefix is how we normally ensure a type is defined. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Sam Ravnborg <sam@ravnborg.org> # for everything in .../bindings/display/ Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Peter Rosin <peda@axentia.se> Acked-by: Bartosz Golaszewski <brgl@bgdev.pl> Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20220519211411.2200720-1-robh@kernel.org
2022-01-11dt-bindings: PCI: snps,dw-pcie-ep: Drop conflicting 'max-functions' schemaRob Herring1-4/+0
'max-functions' is already defined in pci-ep.yaml schema as a uint8 and all users of it expect an uint8. Drop the conflicting schema. Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220107030358.2378221-1-robh@kernel.org
2021-12-14dt-bindings: PCI: designware: Fix 'unevaluatedProperties' warningsRob Herring1-1/+1
With 'unevaluatedProperties' support implemented, there's a number of warnings from the Designware PCIe based bindings: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dt.yaml: pcie@1ffc000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'device_type', 'bus-range', 'ranges', '#interrupt-cells', 'interrupt-map-mask', 'interrupt-map' were unexpected) Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.example.dt.yaml: pcie@1ffc000: Unevaluated properties are not allowed ('clock-names' was unexpected) Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f4000000: Unevaluated properties are not allowed ('bus-range', '#address-cells', '#size-cells', 'device_type', 'ranges', 'num-lanes', '#interrupt-cells', 'interrupts', 'interrupt-names', 'interrupt-map-mask', 'interrupt-map', 'clocks', 'clock-names' were unexpected) Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f4000000: Unevaluated properties are not allowed ('clock-names' was unexpected) Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f5000000: Unevaluated properties are not allowed ('bus-range', '#address-cells', '#size-cells', 'device_type', 'phys', 'ranges', 'num-lanes', '#interrupt-cells', 'interrupts', 'interrupt-names', 'interrupt-map-mask', 'interrupt-map', 'reset-gpios', 'pcie@0,0' were unexpected) Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f5000000: Unevaluated properties are not allowed ('phys', 'hisilicon,clken-gpios' were unexpected) Documentation/devicetree/bindings/pci/intel-gw-pcie.example.dt.yaml: pcie@d0e00000: Unevaluated properties are not allowed ('device_type', '#address-cells', '#size-cells', 'linux,pci-domain', 'bus-range', '#interrupt-cells', 'interrupt-map-mask', 'interrupt-map' were unexpected) Documentation/devicetree/bindings/pci/intel-gw-pcie.example.dt.yaml: pcie@d0e00000: Unevaluated properties are not allowed ('resets', 'phys', 'phy-names', 'reset-assert-ms' were unexpected) Documentation/devicetree/bindings/pci/rockchip-dw-pcie.example.dt.yaml: pcie@fe280000: Unevaluated properties are not allowed ('clock-names', 'msi-map', 'phys', 'phy-names', 'power-domains', 'resets', 'reset-names' were unexpected) Documentation/devicetree/bindings/pci/samsung,exynos-pcie.example.dt.yaml: pcie@15700000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', '#interrupt-cells', 'device_type', 'bus-range', 'ranges', 'interrupt-map-mask', 'interrupt-map' were unexpected) Documentation/devicetree/bindings/pci/samsung,exynos-pcie.example.dt.yaml: pcie@15700000: Unevaluated properties are not allowed ('clock-names', 'phys', 'vdd10-supply', 'vdd18-supply' were unexpected) Documentation/devicetree/bindings/pci/sifive,fu740-pcie.example.dt.yaml: pcie@e00000000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', '#interrupt-cells', 'device_type', 'dma-coherent', 'bus-range', 'ranges', 'interrupts', 'interrupt-parent', 'interrupt-map-mask', 'interrupt-map', 'clock-names', 'clocks' were unexpected) Documentation/devicetree/bindings/pci/sifive,fu740-pcie.example.dt.yaml: pcie@e00000000: Unevaluated properties are not allowed ('dma-coherent', 'clock-names', 'resets', 'pwren-gpios' were unexpected) Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.example.dt.yaml: pcie-ep@66000000: Unevaluated properties are not allowed ('clock-names', 'clocks', 'reset-names', 'resets', 'phy-names', 'phys' were unexpected) Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.example.dt.yaml: pcie@28400000: Unevaluated properties are not allowed ('clock-names' was unexpected) Documentation/devicetree/bindings/pci/toshiba,visconti-pcie.example.dt.yaml: pcie@28400000: Unevaluated properties are not allowed ('device_type', 'bus-range', 'num-viewport', '#address-cells', '#size-cells', '#interrupt-cells', 'ranges', 'interrupt-names', 'interrupt-map-mask', 'interrupt-map', 'max-link-speed' were unexpected) The main problem is that snps,dw-pcie.yaml and snps,dw-pcie-ep.yaml shouldn't set 'unevaluatedProperties: false'. Otherwise, bindings that reference them cannot add additional properties. With that addressed, there's a handful of other undocumented properties to add. Cc: Xiaowei Song <songxiaowei@hisilicon.com> Cc: Binghui Wang <wangbinghui@hisilicon.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Cc: Greentime Hu <greentime.hu@sifive.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Jingoo Han <jingoohan1@gmail.com> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Cc: linux-pci@vger.kernel.org Cc: linux-riscv@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20211206194426.2470080-1-robh@kernel.org
2021-07-19dt-bindings: PCI: add snps,dw-pcie-ep.yamlMauro Carvalho Chehab1-0/+90
Currently, the designware schema is defined on a text file: designware-pcie.txt It contains two separate schemas on it: - snps,dw-pcie This one uses the pci-bus.yaml schema; - snps,dw-pcie-ep This one uses the pci-ep.yaml schema. As the: AllOf: - $ref: <foo> for the endpoint part is different than the PCI one, place it on a separate yaml file. Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Link: https://lore.kernel.org/r/26025b256232c2e4bd91954907b9d92db27199a3.1626608375.git.mchehab+huawei@kernel.org Signed-off-by: Rob Herring <robh@kernel.org>
Copyright © 1996 – 2023 Jason A. Donenfeld. All Rights Reverse Engineered.