diff options
| author |   pirofti <pirofti@openbsd.org> | 2016-04-26 09:01:33 +0000 |
|---|---|---|
| committer | pirofti <pirofti@openbsd.org> | 2016-04-26 09:01:33 +0000 |
| commit | 5cffd0fab60657bcc687ecee270eb4b9b406d28e (patch) | |
| tree | e2f2d9800e20a113803bace240df98f1320d152f /gnu/usr.bin/binutils-2.17/include | |
| parent | Log wcwidth() and mbtowc() failure to make it easier to debug a Unicode (diff) | |
| download | wireguard-openbsd-5cffd0fab60657bcc687ecee270eb4b9b406d28e.tar.xz wireguard-openbsd-5cffd0fab60657bcc687ecee270eb4b9b406d28e.zip | |
Add Octeon specific sync opcodes.
This is needed for proper sili(4) functionality on Octeon II machines.
OK jasper@, visa@
Diffstat (limited to 'gnu/usr.bin/binutils-2.17/include')
| -rw-r--r-- | gnu/usr.bin/binutils-2.17/include/elf/mips.h | 1 | ||||
| -rw-r--r-- | gnu/usr.bin/binutils-2.17/include/opcode/mips.h | 7 |
2 files changed, 8 insertions, 0 deletions
diff --git a/gnu/usr.bin/binutils-2.17/include/elf/mips.h b/gnu/usr.bin/binutils-2.17/include/elf/mips.h index f22bd4d4213..a0b1d606338 100644 --- a/gnu/usr.bin/binutils-2.17/include/elf/mips.h +++ b/gnu/usr.bin/binutils-2.17/include/elf/mips.h @@ -212,6 +212,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext) #define E_MIPS_MACH_4120 0x00870000 #define E_MIPS_MACH_4111 0x00880000 #define E_MIPS_MACH_SB1 0x008a0000 +#define E_MIPS_MACH_OCTEON 0x008b0000 #define E_MIPS_MACH_5400 0x00910000 #define E_MIPS_MACH_5500 0x00980000 #define E_MIPS_MACH_9000 0x00990000 diff --git a/gnu/usr.bin/binutils-2.17/include/opcode/mips.h b/gnu/usr.bin/binutils-2.17/include/opcode/mips.h index 001d55a05ce..c32fb3a8a69 100644 --- a/gnu/usr.bin/binutils-2.17/include/opcode/mips.h +++ b/gnu/usr.bin/binutils-2.17/include/opcode/mips.h @@ -480,6 +480,8 @@ struct mips_opcode /* Chip specific instructions. These are bitmasks. */ +#define INSN_CHIP_MASK 0x0bff0000 + /* MIPS R4650 instruction. */ #define INSN_4650 0x00010000 /* LSI R4010 instruction. */ @@ -502,6 +504,9 @@ struct mips_opcode #define INSN_5500 0x02000000 /* MT ASE */ #define INSN_MT 0x04000000 +/* Cavium Networks Octeon instruction. */ +#define INSN_OCTEON 0x08000000 + /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -549,6 +554,7 @@ struct mips_opcode #define CPU_MIPS64 64 #define CPU_MIPS64R2 65 #define CPU_SB1 12310201 /* octal 'SB', 01. */ +#define CPU_OCTEON 6501 /* Test for membership in an ISA including chip specific ISAs. INSN is pointer to an element of the opcode table; ISA is the specified @@ -570,6 +576,7 @@ struct mips_opcode || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ + || (cpu == CPU_OCTEON && ((insn)->membership & INSN_OCTEON) != 0) \ || 0) /* Please keep this term for easier source merging. */ /* This is a list of macro expanded instructions. |