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author | 2019-09-20 22:42:05 +0000 | |
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committer | 2019-09-20 22:42:05 +0000 | |
commit | ea5e035f4d57ede9f18c82c5c9decc5f46c1925a (patch) | |
tree | 273f759f13d156bb8de0dd5d337baf5f60e744a0 /sys/dev/fdt/sxiccmu_clocks.h | |
parent | Extend the identification and validation of elantech-v4 packets to the (diff) | |
download | wireguard-openbsd-ea5e035f4d57ede9f18c82c5c9decc5f46c1925a.tar.xz wireguard-openbsd-ea5e035f4d57ede9f18c82c5c9decc5f46c1925a.zip |
Add A20 GMAC clocks.
Diffstat (limited to 'sys/dev/fdt/sxiccmu_clocks.h')
-rw-r--r-- | sys/dev/fdt/sxiccmu_clocks.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/sys/dev/fdt/sxiccmu_clocks.h b/sys/dev/fdt/sxiccmu_clocks.h index 558c9a66f32..cc545f40b9b 100644 --- a/sys/dev/fdt/sxiccmu_clocks.h +++ b/sys/dev/fdt/sxiccmu_clocks.h @@ -13,6 +13,8 @@ #define A10_CLK_PLL_PERIPH 15 #define A10_CLK_CPU 20 +#define A10_CLK_AXI 21 +#define A10_CLK_AHB 23 #define A10_CLK_APB1 25 #define A10_CLK_AHB_EHCI0 27 @@ -63,7 +65,7 @@ struct sxiccmu_ccu_bit sun4i_a10_gates[] = { [A10_CLK_AHB_MMC3] = { 0x0060, 11 }, [A10_CLK_AHB_EMAC] = { 0x0060, 17 }, [A10_CLK_AHB_SATA] = { 0x0060, 25 }, - [A10_CLK_AHB_GMAC] = { 0x0064, 17 }, + [A10_CLK_AHB_GMAC] = { 0x0064, 17, A10_CLK_AHB }, [A10_CLK_APB0_PIO] = { 0x0068, 5 }, [A10_CLK_APB1_I2C0] = { 0x006c, 0, A10_CLK_APB1 }, [A10_CLK_APB1_I2C1] = { 0x006c, 1, A10_CLK_APB1 }, |