diff options
Diffstat (limited to 'sys/dev/pci')
| -rw-r--r-- | sys/dev/pci/files.pci | 7 | ||||
| -rw-r--r-- | sys/dev/pci/if_sf.c | 1395 | ||||
| -rw-r--r-- | sys/dev/pci/if_sf_pci.c | 289 | ||||
| -rw-r--r-- | sys/dev/pci/if_sfreg.h | 1057 |
4 files changed, 292 insertions, 2456 deletions
diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci index 18f6070d4d3..199e4768333 100644 --- a/sys/dev/pci/files.pci +++ b/sys/dev/pci/files.pci @@ -1,4 +1,4 @@ -# $OpenBSD: files.pci,v 1.220 2006/11/27 16:47:05 grange Exp $ +# $OpenBSD: files.pci,v 1.221 2006/12/06 20:07:52 martin Exp $ # $NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $ # # Config file and device description for machine-independent PCI code. @@ -398,9 +398,8 @@ attach wb at pci file dev/pci/if_wb.c wb # Adaptec AIC-6915 "Starfire" ethernet -device sf: ether, ifnet, mii, ifmedia -attach sf at pci -file dev/pci/if_sf.c sf +attach sf at pci with sf_pci +file dev/pci/if_sf_pci.c sf_pci # SiS 900/7016 ethernet device sis: ether, ifnet, mii, ifmedia diff --git a/sys/dev/pci/if_sf.c b/sys/dev/pci/if_sf.c deleted file mode 100644 index 77cd73aebe7..00000000000 --- a/sys/dev/pci/if_sf.c +++ /dev/null @@ -1,1395 +0,0 @@ -/* $OpenBSD: if_sf.c,v 1.40 2006/08/22 19:11:46 martin Exp $ */ -/* - * Copyright (c) 1997, 1998, 1999 - * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Bill Paul. - * 4. Neither the name of the author nor the names of any co-contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: src/sys/pci/if_sf.c,v 1.23 2000/07/14 19:11:02 wpaul Exp $ - */ - -/* - * Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD. - * Programming manual is available from: - * http://download.adaptec.com/pdfs/user_guides/aic6915_pg.pdf. - * - * Written by Bill Paul <wpaul@ctr.columbia.edu> - * Department of Electical Engineering - * Columbia University, New York City - */ - -/* - * The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet - * controller designed with flexibility and reducing CPU load in mind. - * The Starfire offers high and low priority buffer queues, a - * producer/consumer index mechanism and several different buffer - * queue and completion queue descriptor types. Any one of a number - * of different driver designs can be used, depending on system and - * OS requirements. This driver makes use of type0 transmit frame - * descriptors (since BSD fragments packets across an mbuf chain) - * and two RX buffer queues prioritized on size (one queue for small - * frames that will fit into a single mbuf, another with full size - * mbuf clusters for everything else). The producer/consumer indexes - * and completion queues are also used. - * - * One downside to the Starfire has to do with alignment: buffer - * queues must be aligned on 256-byte boundaries, and receive buffers - * must be aligned on longword boundaries. The receive buffer alignment - * causes problems on the Alpha platform, where the packet payload - * should be longword aligned. There is no simple way around this. - * - * For receive filtering, the Starfire offers 16 perfect filter slots - * and a 512-bit hash table. - * - * The Starfire has no internal transceiver, relying instead on an - * external MII-based transceiver. Accessing registers on external - * PHYs is done through a special register map rather than with the - * usual bitbang MDIO method. - * - * Accessing the registers on the Starfire is a little tricky. The - * Starfire has a 512K internal register space. When programmed for - * PCI memory mapped mode, the entire register space can be accessed - * directly. However in I/O space mode, only 256 bytes are directly - * mapped into PCI I/O space. The other registers can be accessed - * indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA - * registers inside the 256-byte I/O window. - */ - -#include "bpfilter.h" - -#include <sys/param.h> -#include <sys/systm.h> -#include <sys/mbuf.h> -#include <sys/protosw.h> -#include <sys/socket.h> -#include <sys/ioctl.h> -#include <sys/errno.h> -#include <sys/malloc.h> -#include <sys/kernel.h> -#include <sys/timeout.h> - -#include <net/if.h> -#include <net/if_dl.h> -#include <net/if_types.h> - -#include <netinet/in.h> -#include <netinet/in_systm.h> -#include <netinet/in_var.h> -#include <netinet/ip.h> -#include <netinet/if_ether.h> - -#include <net/if_media.h> - -#if NBPFILTER > 0 -#include <net/bpf.h> -#endif - -#include <uvm/uvm_extern.h> /* for vtophys */ - -#include <sys/device.h> - -#include <dev/mii/mii.h> -#include <dev/mii/miivar.h> - -#include <dev/pci/pcireg.h> -#include <dev/pci/pcivar.h> -#include <dev/pci/pcidevs.h> - -#define SF_USEIOSPACE - -#include <dev/pci/if_sfreg.h> - -int sf_probe(struct device *, void *, void *); -void sf_attach(struct device *, struct device *, void *); -int sf_intr(void *); -void sf_shutdown(void *); -void sf_stats_update(void *); -void sf_rxeof(struct sf_softc *); -void sf_txeof(struct sf_softc *); -int sf_encap(struct sf_softc *, struct sf_tx_bufdesc_type0 *, - struct mbuf *); -void sf_start(struct ifnet *); -int sf_ioctl(struct ifnet *, u_long, caddr_t); -void sf_init(void *); -void sf_stop(struct sf_softc *); -void sf_watchdog(struct ifnet *); -int sf_ifmedia_upd(struct ifnet *); -void sf_ifmedia_sts(struct ifnet *, struct ifmediareq *); -void sf_reset(struct sf_softc *); -int sf_init_rx_ring(struct sf_softc *); -void sf_init_tx_ring(struct sf_softc *); -int sf_newbuf(struct sf_softc *, struct sf_rx_bufdesc_type0 *, - struct mbuf *); -void sf_setmulti(struct sf_softc *); -int sf_setperf(struct sf_softc *, int, caddr_t); -int sf_sethash(struct sf_softc *, caddr_t, int); -#ifdef notdef -int sf_setvlan(struct sf_softc *, int, u_int32_t); -#endif - -u_int8_t sf_read_eeprom(struct sf_softc *, int); - -int sf_miibus_readreg(struct device *, int, int); -void sf_miibus_writereg(struct device *, int, int, int); -void sf_miibus_statchg(struct device *); - -u_int32_t csr_read_4(struct sf_softc *, int); -void csr_write_4(struct sf_softc *, int, u_int32_t); -void sf_txthresh_adjust(struct sf_softc *); - -#define SF_SETBIT(sc, reg, x) \ - csr_write_4(sc, reg, csr_read_4(sc, reg) | x) - -#define SF_CLRBIT(sc, reg, x) \ - csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x) - -u_int32_t csr_read_4(sc, reg) - struct sf_softc *sc; - int reg; -{ - u_int32_t val; - -#ifdef SF_USEIOSPACE - CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); - val = CSR_READ_4(sc, SF_INDIRECTIO_DATA); -#else - val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE)); -#endif - - return(val); -} - -u_int8_t sf_read_eeprom(sc, reg) - struct sf_softc *sc; - int reg; -{ - u_int8_t val; - - val = (csr_read_4(sc, SF_EEADDR_BASE + - (reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF; - - return(val); -} - -void csr_write_4(sc, reg, val) - struct sf_softc *sc; - int reg; - u_int32_t val; -{ -#ifdef SF_USEIOSPACE - CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE); - CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val); -#else - CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val); -#endif - return; -} - -/* - * Copy the address 'mac' into the perfect RX filter entry at - * offset 'idx.' The perfect filter only has 16 entries so do - * some sanity tests. - */ -int sf_setperf(sc, idx, mac) - struct sf_softc *sc; - int idx; - caddr_t mac; -{ - u_int16_t *p; - - if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT) - return(EINVAL); - - if (mac == NULL) - return(EINVAL); - - p = (u_int16_t *)mac; - - csr_write_4(sc, SF_RXFILT_PERFECT_BASE + - (idx * SF_RXFILT_PERFECT_SKIP), htons(p[2])); - csr_write_4(sc, SF_RXFILT_PERFECT_BASE + - (idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1])); - csr_write_4(sc, SF_RXFILT_PERFECT_BASE + - (idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0])); - - return(0); -} - -/* - * Set the bit in the 512-bit hash table that corresponds to the - * specified mac address 'mac.' If 'prio' is nonzero, update the - * priority hash table instead of the filter hash table. - */ -int sf_sethash(sc, mac, prio) - struct sf_softc *sc; - caddr_t mac; - int prio; -{ - u_int32_t h = 0; - - if (mac == NULL) - return(EINVAL); - - h = (ether_crc32_be(mac, ETHER_ADDR_LEN) >> 23) & 0x1FF; - - if (prio) { - SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF + - (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); - } else { - SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF + - (SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF))); - } - - return(0); -} - -#ifdef notdef -/* - * Set a VLAN tag in the receive filter. - */ -int sf_setvlan(sc, idx, vlan) - struct sf_softc *sc; - int idx; - u_int32_t vlan; -{ - if (idx < 0 || idx >> SF_RXFILT_HASH_CNT) - return(EINVAL); - - csr_write_4(sc, SF_RXFILT_HASH_BASE + - (idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan); - - return(0); -} -#endif - -int sf_miibus_readreg(self, phy, reg) - struct device *self; - int phy, reg; -{ - struct sf_softc *sc = (struct sf_softc *)self; - int i; - u_int32_t val = 0; - - for (i = 0; i < SF_TIMEOUT; i++) { - val = csr_read_4(sc, SF_PHY_REG(phy, reg)); - if (val & SF_MII_DATAVALID) - break; - } - - if (i == SF_TIMEOUT) - return(0); - - if ((val & 0x0000FFFF) == 0xFFFF) - return(0); - - return(val & 0x0000FFFF); -} - -void sf_miibus_writereg(self, phy, reg, val) - struct device *self; - int phy, reg, val; -{ - struct sf_softc *sc = (struct sf_softc *)self; - int i; - int busy; - - csr_write_4(sc, SF_PHY_REG(phy, reg), val); - - for (i = 0; i < SF_TIMEOUT; i++) { - busy = csr_read_4(sc, SF_PHY_REG(phy, reg)); - if (!(busy & SF_MII_BUSY)) - break; - } - - return; -} - -void sf_miibus_statchg(self) - struct device *self; -{ - struct sf_softc *sc = (struct sf_softc *)self; - struct mii_data *mii; - - mii = &sc->sc_mii; - - if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { - SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); - csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX); - } else { - SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX); - csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX); - } - - return; -} - -void sf_setmulti(sc) - struct sf_softc *sc; -{ - struct ifnet *ifp; - int i; - struct arpcom *ac = &sc->arpcom; - struct ether_multi *enm; - struct ether_multistep step; - u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 }; - - ifp = &sc->arpcom.ac_if; - - /* First zot all the existing filters. */ - for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++) - sf_setperf(sc, i, (char *)&dummy); - for (i = SF_RXFILT_HASH_BASE; - i < (SF_RXFILT_HASH_MAX + 1); i += 4) - csr_write_4(sc, i, 0); - SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); - - /* Now program new ones. */ -allmulti: - if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { - SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI); - } else { - i = 1; - /* First find the tail of the list. */ - ETHER_FIRST_MULTI(step, ac, enm); - - /* Now traverse the list backwards. */ - while (enm != NULL) { - if (bcmp(enm->enm_addrlo, enm->enm_addrhi, - ETHER_ADDR_LEN)) { - ifp->if_flags |= IFF_ALLMULTI; - goto allmulti; - } - - /* if (enm->enm_addrlo->sa_family != AF_LINK) - continue; */ - /* - * Program the first 15 multicast groups - * into the perfect filter. For all others, - * use the hash table. - */ - if (i < SF_RXFILT_PERFECT_CNT) { - sf_setperf(sc, i, enm->enm_addrlo); - i++; - continue; - } - - sf_sethash(sc, enm->enm_addrlo, 0); - ETHER_NEXT_MULTI(step, enm); - } - } - - return; -} - -/* - * Set media options. - */ -int sf_ifmedia_upd(ifp) - struct ifnet *ifp; -{ - struct sf_softc *sc; - struct mii_data *mii; - - sc = ifp->if_softc; - mii = &sc->sc_mii; - sc->sf_link = 0; - if (mii->mii_instance) { - struct mii_softc *miisc; - LIST_FOREACH(miisc, &mii->mii_phys, mii_list) - mii_phy_reset(miisc); - } - mii_mediachg(mii); - - return(0); -} - -/* - * Report current media status. - */ -void sf_ifmedia_sts(ifp, ifmr) - struct ifnet *ifp; - struct ifmediareq *ifmr; -{ - struct sf_softc *sc; - struct mii_data *mii; - - sc = ifp->if_softc; - mii = &sc->sc_mii; - - mii_pollstat(mii); - ifmr->ifm_active = mii->mii_media_active; - ifmr->ifm_status = mii->mii_media_status; - - return; -} - -int sf_ioctl(ifp, command, data) - struct ifnet *ifp; - u_long command; - caddr_t data; -{ - struct sf_softc *sc = ifp->if_softc; - struct ifreq *ifr = (struct ifreq *) data; - struct ifaddr *ifa = (struct ifaddr *)data; - struct mii_data *mii; - int s, error = 0; - - s = splnet(); - - if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { - splx(s); - return error; - } - - switch(command) { - case SIOCSIFADDR: - ifp->if_flags |= IFF_UP; - switch (ifa->ifa_addr->sa_family) { - case AF_INET: - sf_init(sc); - arp_ifinit(&sc->arpcom, ifa); - break; - default: - sf_init(sc); - break; - } - break; - case SIOCSIFFLAGS: - if (ifp->if_flags & IFF_UP) { - if (ifp->if_flags & IFF_RUNNING && - ifp->if_flags & IFF_PROMISC && - !(sc->sf_if_flags & IFF_PROMISC)) { - SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); - } else if (ifp->if_flags & IFF_RUNNING && - !(ifp->if_flags & IFF_PROMISC) && - sc->sf_if_flags & IFF_PROMISC) { - SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); - } else if (!(ifp->if_flags & IFF_RUNNING)) - sf_init(sc); - } else { - if (ifp->if_flags & IFF_RUNNING) - sf_stop(sc); - } - sc->sf_if_flags = ifp->if_flags; - error = 0; - break; - case SIOCADDMULTI: - case SIOCDELMULTI: - error = (command == SIOCADDMULTI) ? - ether_addmulti(ifr, &sc->arpcom) : - ether_delmulti(ifr, &sc->arpcom); - - if (error == ENETRESET) { - /* - * Multicast list has changed; set the hardware - * filter accordingly. - */ - if (ifp->if_flags & IFF_RUNNING) - sf_setmulti(sc); - error = 0; - } - break; - case SIOCGIFMEDIA: - case SIOCSIFMEDIA: - mii = &sc->sc_mii; - error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); - break; - default: - error = ENOTTY; - break; - } - - splx(s); - - return(error); -} - -void sf_reset(sc) - struct sf_softc *sc; -{ - int i; - - csr_write_4(sc, SF_GEN_ETH_CTL, 0); - SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); - DELAY(1000); - SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET); - - SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET); - - for (i = 0; i < SF_TIMEOUT; i++) { - DELAY(10); - if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET)) - break; - } - - if (i == SF_TIMEOUT) - printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); - - /* Wait a little while for the chip to get its brains in order. */ - DELAY(1000); - return; -} - -/* - * Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device - * IDs against our list and return a device name if we find a match. - * We also check the subsystem ID so that we can identify exactly which - * NIC has been found, if possible. - */ -int sf_probe(parent, match, aux) - struct device *parent; - void *match; - void *aux; -{ - struct pci_attach_args *pa = (struct pci_attach_args *)aux; - - if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ADP && - PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ADP_AIC6915) - return(1); - - return(0); -} - -/* - * Attach the interface. Allocate softc structures, do ifmedia - * setup and ethernet/BPF attach. - */ -void sf_attach(parent, self, aux) - struct device *parent, *self; - void *aux; -{ - int i; - const char *intrstr = NULL; - u_int32_t command; - struct sf_softc *sc = (struct sf_softc *)self; - struct pci_attach_args *pa = aux; - pci_chipset_tag_t pc = pa->pa_pc; - pci_intr_handle_t ih; - struct ifnet *ifp; - bus_size_t size; - - /* - * Handle power management nonsense. - */ - command = pci_conf_read(pc, pa->pa_tag, SF_PCI_CAPID) & 0x000000FF; - if (command == 0x01) { - - command = pci_conf_read(pc, pa->pa_tag, SF_PCI_PWRMGMTCTRL); - if (command & SF_PSTATE_MASK) { - u_int32_t iobase, membase, irq; - - /* Save important PCI config data. */ - iobase = pci_conf_read(pc, pa->pa_tag, SF_PCI_LOIO); - membase = pci_conf_read(pc, pa->pa_tag, SF_PCI_LOMEM); - irq = pci_conf_read(pc, pa->pa_tag, SF_PCI_INTLINE); - - /* Reset the power state. */ - printf("%s: chip is in D%d power mode -- setting to D0\n", - sc->sc_dev.dv_xname, command & SF_PSTATE_MASK); - command &= 0xFFFFFFFC; - pci_conf_write(pc, pa->pa_tag, SF_PCI_PWRMGMTCTRL, command); - - /* Restore PCI config data. */ - pci_conf_write(pc, pa->pa_tag, SF_PCI_LOIO, iobase); - pci_conf_write(pc, pa->pa_tag, SF_PCI_LOMEM, membase); - pci_conf_write(pc, pa->pa_tag, SF_PCI_INTLINE, irq); - } - } - - /* - * Map control/status registers. - */ - -#ifdef SF_USEIOSPACE - if (pci_mapreg_map(pa, SF_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, - &sc->sf_btag, &sc->sf_bhandle, NULL, &size, 0)) { - printf(": can't map I/O space\n"); - return; - } -#else - if (pci_mapreg_map(pa, SF_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, - &sc->sf_btag, &sc->sf_bhandle, NULL, &size, 0)){ - printf(": can't map mem space\n"); - return; - } -#endif - - /* Allocate interrupt */ - if (pci_intr_map(pa, &ih)) { - printf(": couldn't map interrupt\n"); - goto fail_1; - } - intrstr = pci_intr_string(pc, ih); - sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, sf_intr, sc, - self->dv_xname); - if (sc->sc_ih == NULL) { - printf(": couldn't establish interrupt"); - if (intrstr != NULL) - printf(" at %s", intrstr); - printf("\n"); - goto fail_1; - } - printf(": %s", intrstr); - - /* Reset the adapter. */ - sf_reset(sc); - - /* - * Get station address from the EEPROM. - */ - for (i = 0; i < ETHER_ADDR_LEN; i++) - sc->arpcom.ac_enaddr[i] = - sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i); - - printf(", address %s\n", ether_sprintf(sc->arpcom.ac_enaddr)); - - /* Allocate the descriptor queues. */ - sc->sf_ldata_ptr = malloc(sizeof(struct sf_list_data) + 8, - M_DEVBUF, M_NOWAIT); - if (sc->sf_ldata_ptr == NULL) { - printf(": no memory for list buffers!\n"); - goto fail_2; - } - - sc->sf_ldata = (struct sf_list_data *)sc->sf_ldata_ptr; - bzero(sc->sf_ldata, sizeof(struct sf_list_data)); - - ifp = &sc->arpcom.ac_if; - ifp->if_softc = sc; - ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; - ifp->if_ioctl = sf_ioctl; - ifp->if_start = sf_start; - ifp->if_watchdog = sf_watchdog; - ifp->if_baudrate = 10000000; - IFQ_SET_MAXLEN(&ifp->if_snd, SF_TX_DLIST_CNT - 1); - IFQ_SET_READY(&ifp->if_snd); - bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); - - /* - * Initialize our media structures and probe the MII. - */ - sc->sc_mii.mii_ifp = ifp; - sc->sc_mii.mii_readreg = sf_miibus_readreg; - sc->sc_mii.mii_writereg = sf_miibus_writereg; - sc->sc_mii.mii_statchg = sf_miibus_statchg; - ifmedia_init(&sc->sc_mii.mii_media, 0, sf_ifmedia_upd, sf_ifmedia_sts); - mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY, - 0); - if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { - ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); - ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); - } else - ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); - - /* - * Call MI attach routines. - */ - if_attach(ifp); - ether_ifattach(ifp); - - shutdownhook_establish(sf_shutdown, sc); - return; - -fail_2: - pci_intr_disestablish(pc, sc->sc_ih); - -fail_1: - bus_space_unmap(sc->sf_btag, sc->sf_bhandle, size); -} - -int sf_init_rx_ring(sc) - struct sf_softc *sc; -{ - struct sf_list_data *ld; - int i; - - ld = sc->sf_ldata; - - bzero((char *)ld->sf_rx_dlist_big, - sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT); - bzero((char *)ld->sf_rx_clist, - sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT); - - for (i = 0; i < SF_RX_DLIST_CNT; i++) { - if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS) - return(ENOBUFS); - } - - return(0); -} - -void sf_init_tx_ring(sc) - struct sf_softc *sc; -{ - struct sf_list_data *ld; - int i; - - ld = sc->sf_ldata; - - bzero((char *)ld->sf_tx_dlist, - sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT); - bzero((char *)ld->sf_tx_clist, - sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT); - - for (i = 0; i < SF_TX_DLIST_CNT; i++) - ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID; - for (i = 0; i < SF_TX_CLIST_CNT; i++) - ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX; - - ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1; - sc->sf_tx_cnt = 0; - - return; -} - -int sf_newbuf(sc, c, m) - struct sf_softc *sc; - struct sf_rx_bufdesc_type0 *c; - struct mbuf *m; -{ - struct mbuf *m_new = NULL; - - if (m == NULL) { - MGETHDR(m_new, M_DONTWAIT, MT_DATA); - if (m_new == NULL) - return(ENOBUFS); - - MCLGET(m_new, M_DONTWAIT); - if (!(m_new->m_flags & M_EXT)) { - m_freem(m_new); - return(ENOBUFS); - } - m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; - } else { - m_new = m; - m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; - m_new->m_data = m_new->m_ext.ext_buf; - } - - m_adj(m_new, sizeof(u_int64_t)); - - c->sf_mbuf = m_new; - c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, vaddr_t))); - c->sf_valid = 1; - - return(0); -} - -/* - * The starfire is programmed to use 'normal' mode for packet reception, - * which means we use the consumer/producer model for both the buffer - * descriptor queue and the completion descriptor queue. The only problem - * with this is that it involves a lot of register accesses: we have to - * read the RX completion consumer and producer indexes and the RX buffer - * producer index, plus the RX completion consumer and RX buffer producer - * indexes have to be updated. It would have been easier if Adaptec had - * put each index in a separate register, especially given that the damn - * NIC has a 512K register space. - * - * In spite of all the lovely features that Adaptec crammed into the 6915, - * it is marred by one truly stupid design flaw, which is that receive - * buffer addresses must be aligned on a longword boundary. This forces - * the packet payload to be unaligned, which is suboptimal on the x86 and - * completely unuseable on the Alpha. Our only recourse is to copy received - * packets into properly aligned buffers before handing them off. - */ - -void sf_rxeof(sc) - struct sf_softc *sc; -{ - struct mbuf *m; - struct ifnet *ifp; - struct sf_rx_bufdesc_type0 *desc; - struct sf_rx_cmpdesc_type3 *cur_rx; - u_int32_t rxcons, rxprod; - int cmpprodidx, cmpconsidx, bufprodidx; - - ifp = &sc->arpcom.ac_if; - - rxcons = csr_read_4(sc, SF_CQ_CONSIDX); - rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1); - cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX)); - cmpconsidx = SF_IDX_LO(rxcons); - bufprodidx = SF_IDX_LO(rxprod); - - while (cmpconsidx != cmpprodidx) { - struct mbuf *m0; - - cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx]; - desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx]; - m = desc->sf_mbuf; - SF_INC(cmpconsidx, SF_RX_CLIST_CNT); - SF_INC(bufprodidx, SF_RX_DLIST_CNT); - - if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) { - ifp->if_ierrors++; - sf_newbuf(sc, desc, m); - continue; - } - - m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, - cur_rx->sf_len + ETHER_ALIGN, 0, ifp, NULL); - sf_newbuf(sc, desc, m); - if (m0 == NULL) { - ifp->if_ierrors++; - continue; - } - m_adj(m0, ETHER_ALIGN); - m = m0; - - ifp->if_ipackets++; - -#if NBPFILTER > 0 - if (ifp->if_bpf) - bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); -#endif - - /* pass it on. */ - ether_input_mbuf(ifp, m); - } - - csr_write_4(sc, SF_CQ_CONSIDX, - (rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx); - csr_write_4(sc, SF_RXDQ_PTR_Q1, - (rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx); - - return; -} - -/* - * Read the transmit status from the completion queue and release - * mbufs. Note that the buffer descriptor index in the completion - * descriptor is an offset from the start of the transmit buffer - * descriptor list in bytes. This is important because the manual - * gives the impression that it should match the producer/consumer - * index, which is the offset in 8 byte blocks. - */ -void sf_txeof(sc) - struct sf_softc *sc; -{ - int txcons, cmpprodidx, cmpconsidx; - struct sf_tx_cmpdesc_type1 *cur_cmp; - struct sf_tx_bufdesc_type0 *cur_tx; - struct ifnet *ifp; - - ifp = &sc->arpcom.ac_if; - - txcons = csr_read_4(sc, SF_CQ_CONSIDX); - cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX)); - cmpconsidx = SF_IDX_HI(txcons); - - while (cmpconsidx != cmpprodidx) { - cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx]; - cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7]; - - if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK) - ifp->if_opackets++; - else { - if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN) - sf_txthresh_adjust(sc); - ifp->if_oerrors++; - } - - sc->sf_tx_cnt--; - if (cur_tx->sf_mbuf != NULL) { - m_freem(cur_tx->sf_mbuf); - cur_tx->sf_mbuf = NULL; - } else - break; - SF_INC(cmpconsidx, SF_TX_CLIST_CNT); - } - - ifp->if_timer = 0; - ifp->if_flags &= ~IFF_OACTIVE; - - csr_write_4(sc, SF_CQ_CONSIDX, - (txcons & ~SF_CQ_CONSIDX_TXQ) | - ((cmpconsidx << 16) & 0xFFFF0000)); - - return; -} - -void -sf_txthresh_adjust(sc) - struct sf_softc *sc; -{ - u_int32_t txfctl; - u_int8_t txthresh; - - txfctl = csr_read_4(sc, SF_TX_FRAMCTL); - txthresh = txfctl & SF_TXFRMCTL_TXTHRESH; - if (txthresh < 0xFF) { - txthresh++; - txfctl &= ~SF_TXFRMCTL_TXTHRESH; - txfctl |= txthresh; -#ifdef SF_DEBUG - printf("%s: tx underrun, increasing tx threshold to %d bytes\n", - sc->sc_dev.dv_xname, txthresh * 4); -#endif - csr_write_4(sc, SF_TX_FRAMCTL, txfctl); - } - - return; -} - -int sf_intr(arg) - void *arg; -{ - struct sf_softc *sc; - struct ifnet *ifp; - u_int32_t status; - int claimed = 0; - - sc = arg; - ifp = &sc->arpcom.ac_if; - - if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) - return claimed; - - /* Disable interrupts. */ - csr_write_4(sc, SF_IMR, 0x00000000); - - for (;;) { - status = csr_read_4(sc, SF_ISR); - if (status) - csr_write_4(sc, SF_ISR, status); - - if (!(status & SF_INTRS)) - break; - - claimed = 1; - - if (status & SF_ISR_RXDQ1_DMADONE) - sf_rxeof(sc); - - if (status & SF_ISR_TX_TXDONE || - status & SF_ISR_TX_DMADONE || - status & SF_ISR_TX_QUEUEDONE || - status & SF_ISR_TX_LOFIFO) - sf_txeof(sc); - - if (status & SF_ISR_TX_LOFIFO) - sf_txthresh_adjust(sc); - - if (status & SF_ISR_ABNORMALINTR) { - if (status & SF_ISR_STATSOFLOW) { - timeout_del(&sc->sc_stats_tmo); - sf_stats_update(sc); - } else - sf_init(sc); - } - } - - /* Re-enable interrupts. */ - csr_write_4(sc, SF_IMR, SF_INTRS); - - if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) - sf_start(ifp); - - return claimed; -} - -void sf_init(xsc) - void *xsc; -{ - struct sf_softc *sc = xsc; - struct ifnet *ifp = &sc->arpcom.ac_if; - struct mii_data *mii; - int i, s; - - s = splnet(); - - mii = &sc->sc_mii; - - sf_stop(sc); - sf_reset(sc); - - /* Init all the receive filter registers */ - for (i = SF_RXFILT_PERFECT_BASE; - i < (SF_RXFILT_HASH_MAX + 1); i += 4) - csr_write_4(sc, i, 0); - - /* Empty stats counter registers. */ - for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++) - csr_write_4(sc, SF_STATS_BASE + - (i + sizeof(u_int32_t)), 0); - - /* Init our MAC address */ - csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); - csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); - sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr); - - if (sf_init_rx_ring(sc) == ENOBUFS) { - printf("%s: initialization failed: no " - "memory for rx buffers\n", sc->sc_dev.dv_xname); - splx(s); - return; - } - - sf_init_tx_ring(sc); - - csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN); - - /* If we want promiscuous mode, set the allframes bit. */ - if (ifp->if_flags & IFF_PROMISC) { - SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); - } else { - SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC); - } - - if (ifp->if_flags & IFF_BROADCAST) { - SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); - } else { - SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD); - } - - /* - * Load the multicast filter. - */ - sf_setmulti(sc); - - /* Init the completion queue indexes */ - csr_write_4(sc, SF_CQ_CONSIDX, 0); - csr_write_4(sc, SF_CQ_PRODIDX, 0); - - /* Init the RX completion queue */ - csr_write_4(sc, SF_RXCQ_CTL_1, - vtophys((vaddr_t)sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR); - SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3); - - /* Init RX DMA control. */ - SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS); - - /* Init the RX buffer descriptor queue. */ - csr_write_4(sc, SF_RXDQ_ADDR_Q1, - vtophys((vaddr_t)sc->sf_ldata->sf_rx_dlist_big)); - csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES); - csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1); - - /* Init the TX completion queue */ - csr_write_4(sc, SF_TXCQ_CTL, - vtophys((vaddr_t)sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR); - - /* Init the TX buffer descriptor queue. */ - csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, - vtophys((vaddr_t)sc->sf_ldata->sf_tx_dlist)); - SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX); - csr_write_4(sc, SF_TXDQ_CTL, - SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES); - SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP); - - /* Enable autopadding of short TX frames. */ - SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD); - - /* Enable interrupts. */ - csr_write_4(sc, SF_IMR, SF_INTRS); - SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB); - - /* Enable the RX and TX engines. */ - SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB); - SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB); - - sf_ifmedia_upd(ifp); - - ifp->if_flags |= IFF_RUNNING; - ifp->if_flags &= ~IFF_OACTIVE; - - splx(s); - - timeout_set(&sc->sc_stats_tmo, sf_stats_update, sc); - timeout_add(&sc->sc_stats_tmo, hz); - - return; -} - -int sf_encap(sc, c, m_head) - struct sf_softc *sc; - struct sf_tx_bufdesc_type0 *c; - struct mbuf *m_head; -{ - int frag = 0; - struct sf_frag *f = NULL; - struct mbuf *m; - - m = m_head; - - for (m = m_head, frag = 0; m != NULL; m = m->m_next) { - if (m->m_len != 0) { - if (frag == SF_MAXFRAGS) - break; - f = &c->sf_frags[frag]; - if (frag == 0) - f->sf_pktlen = m_head->m_pkthdr.len; - f->sf_fraglen = m->m_len; - f->sf_addr = vtophys(mtod(m, vaddr_t)); - frag++; - } - } - - if (m != NULL) { - struct mbuf *m_new = NULL; - - MGETHDR(m_new, M_DONTWAIT, MT_DATA); - if (m_new == NULL) { - printf("%s: no memory for tx list\n", - sc->sc_dev.dv_xname); - return(1); - } - - if (m_head->m_pkthdr.len > MHLEN) { - MCLGET(m_new, M_DONTWAIT); - if (!(m_new->m_flags & M_EXT)) { - m_freem(m_new); - printf("%s: no memory for tx list\n", - sc->sc_dev.dv_xname); - return(1); - } - } - m_copydata(m_head, 0, m_head->m_pkthdr.len, - mtod(m_new, caddr_t)); - m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; - m_freem(m_head); - m_head = m_new; - f = &c->sf_frags[0]; - f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len; - f->sf_addr = vtophys(mtod(m_head, vaddr_t)); - frag = 1; - } - - c->sf_mbuf = m_head; - c->sf_id = SF_TX_BUFDESC_ID; - c->sf_fragcnt = frag; - c->sf_intr = 1; - c->sf_caltcp = 0; - c->sf_crcen = 1; - - return(0); -} - -void sf_start(ifp) - struct ifnet *ifp; -{ - struct sf_softc *sc; - struct sf_tx_bufdesc_type0 *cur_tx = NULL; - struct mbuf *m_head = NULL; - int i, txprod; - - sc = ifp->if_softc; - - if (!sc->sf_link && ifp->if_snd.ifq_len < 10) - return; - - if (ifp->if_flags & IFF_OACTIVE) - return; - - txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); - i = SF_IDX_HI(txprod) >> 4; - - if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { - printf("%s: TX ring full, resetting\n", sc->sc_dev.dv_xname); - sf_init(sc); - txprod = csr_read_4(sc, SF_TXDQ_PRODIDX); - i = SF_IDX_HI(txprod) >> 4; - } - - while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) { - if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) { - ifp->if_flags |= IFF_OACTIVE; - cur_tx = NULL; - break; - } - IFQ_DEQUEUE(&ifp->if_snd, m_head); - if (m_head == NULL) - break; - - cur_tx = &sc->sf_ldata->sf_tx_dlist[i]; - if (sf_encap(sc, cur_tx, m_head)) { - m_freem(m_head); - continue; - } - -#if NBPFILTER > 0 - /* - * If there's a BPF listener, bounce a copy of this frame - * to him. - */ - if (ifp->if_bpf) - bpf_mtap(ifp->if_bpf, cur_tx->sf_mbuf, - BPF_DIRECTION_OUT); -#endif - - SF_INC(i, SF_TX_DLIST_CNT); - sc->sf_tx_cnt++; - /* - * Don't let the TX DMA queue get too full. - */ - if (sc->sf_tx_cnt > 64) - break; - } - - if (cur_tx == NULL) - return; - - /* Transmit */ - csr_write_4(sc, SF_TXDQ_PRODIDX, - (txprod & ~SF_TXDQ_PRODIDX_HIPRIO) | - ((i << 20) & 0xFFFF0000)); - - ifp->if_timer = 5; - - return; -} - -void sf_stop(sc) - struct sf_softc *sc; -{ - int i; - struct ifnet *ifp; - - ifp = &sc->arpcom.ac_if; - - timeout_del(&sc->sc_stats_tmo); - - ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); - - csr_write_4(sc, SF_GEN_ETH_CTL, 0); - csr_write_4(sc, SF_CQ_CONSIDX, 0); - csr_write_4(sc, SF_CQ_PRODIDX, 0); - csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0); - csr_write_4(sc, SF_RXDQ_CTL_1, 0); - csr_write_4(sc, SF_RXDQ_PTR_Q1, 0); - csr_write_4(sc, SF_TXCQ_CTL, 0); - csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0); - csr_write_4(sc, SF_TXDQ_CTL, 0); - sf_reset(sc); - - sc->sf_link = 0; - - for (i = 0; i < SF_RX_DLIST_CNT; i++) { - if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) { - m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf); - sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL; - } - } - - for (i = 0; i < SF_TX_DLIST_CNT; i++) { - if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) { - m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf); - sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL; - } - } - - return; -} - -/* - * Note: it is important that this function not be interrupted. We - * use a two-stage register access scheme: if we are interrupted in - * between setting the indirect address register and reading from the - * indirect data register, the contents of the address register could - * be changed out from under us. - */ -void sf_stats_update(xsc) - void *xsc; -{ - struct sf_softc *sc; - struct ifnet *ifp; - struct mii_data *mii; - struct sf_stats stats; - u_int32_t *ptr; - int i, s; - - s = splnet(); - - sc = xsc; - ifp = &sc->arpcom.ac_if; - mii = &sc->sc_mii; - - ptr = (u_int32_t *)&stats; - for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) - ptr[i] = csr_read_4(sc, SF_STATS_BASE + - (i + sizeof(u_int32_t))); - - for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++) - csr_write_4(sc, SF_STATS_BASE + - (i + sizeof(u_int32_t)), 0); - - ifp->if_collisions += stats.sf_tx_single_colls + - stats.sf_tx_multi_colls + stats.sf_tx_excess_colls; - - mii_tick(mii); - if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE && - IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { - sc->sf_link++; - if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) - sf_start(ifp); - } - - splx(s); - - timeout_add(&sc->sc_stats_tmo, hz); - - return; -} - -void sf_watchdog(ifp) - struct ifnet *ifp; -{ - struct sf_softc *sc; - - sc = ifp->if_softc; - - ifp->if_oerrors++; - printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); - - sf_stop(sc); - sf_reset(sc); - sf_init(sc); - - if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) - sf_start(ifp); - - return; -} - -void sf_shutdown(v) - void *v; -{ - struct sf_softc *sc = (struct sf_softc *)v; - - sf_stop(sc); -} - -struct cfattach sf_ca = { - sizeof(struct sf_softc), sf_probe, sf_attach -}; - -struct cfdriver sf_cd = { - 0, "sf", DV_IFNET -}; - diff --git a/sys/dev/pci/if_sf_pci.c b/sys/dev/pci/if_sf_pci.c new file mode 100644 index 00000000000..483b3963402 --- /dev/null +++ b/sys/dev/pci/if_sf_pci.c @@ -0,0 +1,289 @@ +/* $OpenBSD: if_sf_pci.c,v 1.1 2006/12/06 20:07:52 martin Exp $ */ +/* $NetBSD: if_sf_pci.c,v 1.10 2006/06/17 23:34:27 christos Exp $ */ + +/*- + * Copyright (c) 2001 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/* + * PCI bus front-end for the Adaptec AIC-6915 (``Starfire'') + * 10/100 Ethernet controller. + */ + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/mbuf.h> +#include <sys/malloc.h> +#include <sys/kernel.h> +#include <sys/socket.h> +#include <sys/ioctl.h> +#include <sys/errno.h> +#include <sys/device.h> + +#include <net/if.h> +#include <net/if_dl.h> +#include <net/if_types.h> + +#ifdef INET +#include <netinet/in.h> +#include <netinet/in_systm.h> +#include <netinet/in_var.h> +#include <netinet/ip.h> +#include <netinet/if_ether.h> +#endif + +#include <net/if_media.h> + +#include <machine/bus.h> +#include <machine/intr.h> + +#include <dev/mii/miivar.h> + +#include <dev/ic/aic6915.h> + +#include <dev/pci/pcireg.h> +#include <dev/pci/pcivar.h> +#include <dev/pci/pcidevs.h> + +struct sf_pci_softc { + struct sf_softc sc_starfire; /* read Starfire softc */ + + /* PCI-specific goo. */ + void *sc_ih; /* interrupt handle */ +}; + +static int sf_pci_match(struct device *, void *, void *); +static void sf_pci_attach(struct device *, struct device *, void *); + +struct cfattach sf_pci_ca = { + sizeof(struct sf_pci_softc), sf_pci_match, sf_pci_attach +}; + +struct sf_pci_product { + uint32_t spp_vendor; /* PCI vendor ID */ + uint32_t spp_product; /* PCI product ID */ + const char *spp_name; /* product name */ + const struct sf_pci_product *spp_subsys; /* subsystm IDs */ +}; + +static const struct sf_pci_product sf_subsys_adaptec[] = { + /* ANA-62011 (rev 0) Single port 10/100 64-bit */ + { PCI_VENDOR_ADP, 0x0008, + "ANA-62011 (rev 0) 10/100 Ethernet", NULL }, + + /* ANA-62011 (rev 1) Single port 10/100 64-bit */ + { PCI_VENDOR_ADP, 0x0009, + "ANA-62011 (rev 1) 10/100 Ethernet", NULL }, + + /* ANA-62022 Dual port 10/100 64-bit */ + { PCI_VENDOR_ADP, 0x0010, + "ANA-62022 10/100 Ethernet", NULL }, + + /* ANA-62044 (rev 0) Quad port 10/100 64-bit */ + { PCI_VENDOR_ADP, 0x0018, + "ANA-62044 (rev 0) 10/100 Ethernet", NULL }, + + /* ANA-62044 (rev 1) Quad port 10/100 64-bit */ + { PCI_VENDOR_ADP, 0x0019, + "ANA-62044 (rev 1) 10/100 Ethernet", NULL }, + + /* ANA-62020 Single port 100baseFX 64-bit */ + { PCI_VENDOR_ADP, 0x0020, + "ANA-62020 100baseFX Ethernet", NULL }, + + /* ANA-69011 Single port 10/100 32-bit */ + { PCI_VENDOR_ADP, 0x0028, + "ANA-69011 10/100 Ethernet", NULL }, + + { 0, 0, + NULL, NULL }, +}; + +static const struct sf_pci_product sf_pci_products[] = { + { PCI_VENDOR_ADP, PCI_PRODUCT_ADP_AIC6915, + "AIC-6915 10/100 Ethernet", sf_subsys_adaptec }, + + { 0, 0, + NULL, NULL }, +}; + +static const struct sf_pci_product * +sf_pci_lookup(const struct pci_attach_args *pa) +{ + const struct sf_pci_product *spp, *subspp; + pcireg_t subsysid; + + for (spp = sf_pci_products; spp->spp_name != NULL; spp++) { + if (PCI_VENDOR(pa->pa_id) == spp->spp_vendor && + PCI_PRODUCT(pa->pa_id) == spp->spp_product) { + subsysid = pci_conf_read(pa->pa_pc, pa->pa_tag, + PCI_SUBSYS_ID_REG); + for (subspp = spp->spp_subsys; + subspp->spp_name != NULL; subspp++) { + if (PCI_VENDOR(subsysid) == + subspp->spp_vendor || + PCI_PRODUCT(subsysid) == + subspp->spp_product) { + return (subspp); + } + } + return (spp); + } + } + + return (NULL); +} + +static int +sf_pci_match(struct device *parent, void *match, void *aux) +{ + struct pci_attach_args *pa = aux; + + if (sf_pci_lookup(pa) != NULL) + return (1); + + return (0); +} + +static void +sf_pci_attach(struct device *parent, struct device *self, void *aux) +{ + struct sf_pci_softc *psc = (void *) self; + struct sf_softc *sc = &psc->sc_starfire; + struct pci_attach_args *pa = aux; + pci_intr_handle_t ih; + const char *intrstr = NULL; + const struct sf_pci_product *spp; + bus_space_tag_t iot, memt; + bus_space_handle_t ioh, memh; + pcireg_t reg; + int pmreg, ioh_valid, memh_valid; + + spp = sf_pci_lookup(pa); + if (spp == NULL) { + printf("\n"); + panic("sf_pci_attach: impossible"); + } + + printf(": %s, rev. %d", spp->spp_name, PCI_REVISION(pa->pa_class)); + + if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PWRMGMT, + &pmreg, 0)) { + reg = pci_conf_read(pa->pa_pc, pa->pa_tag, pmreg + PCI_PMCSR); + switch (reg & PCI_PMCSR_STATE_MASK) { + case PCI_PMCSR_STATE_D1: + case PCI_PMCSR_STATE_D2: + printf(": waking up from power state D%d\n%s", + reg & PCI_PMCSR_STATE_MASK, sc->sc_dev.dv_xname); + pci_conf_write(pa->pa_pc, pa->pa_tag, pmreg + PCI_PMCSR, + (reg & ~PCI_PMCSR_STATE_MASK) | + PCI_PMCSR_STATE_D0); + break; + + case PCI_PMCSR_STATE_D3: + printf("%s: unable to wake up from power state D3\n", + sc->sc_dev.dv_xname); + pci_conf_write(pa->pa_pc, pa->pa_tag, pmreg + PCI_PMCSR, + (reg & ~PCI_PMCSR_STATE_MASK) | + PCI_PMCSR_STATE_D0); + return; + } + } + + /* + * Map the device. + */ + reg = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SF_PCI_MEMBA); + switch (reg) { + case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: + case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: + memh_valid = (pci_mapreg_map(pa, SF_PCI_MEMBA, + reg, 0, &memt, &memh, NULL, NULL, 0) == 0); + break; + default: + memh_valid = 0; + } + + ioh_valid = (pci_mapreg_map(pa, + (reg == (PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT)) ? + SF_PCI_IOBA : SF_PCI_IOBA - 0x04, + PCI_MAPREG_TYPE_IO, 0, + &iot, &ioh, NULL, NULL, 0) == 0); + + if (memh_valid) { + sc->sc_st = memt; + sc->sc_sh = memh; + sc->sc_iomapped = 0; + } else if (ioh_valid) { + sc->sc_st = iot; + sc->sc_sh = ioh; + sc->sc_iomapped = 1; + } else { + printf("%s: unable to map device registers\n", + sc->sc_dev.dv_xname); + return; + } + + sc->sc_dmat = pa->pa_dmat; + + /* Make sure bus mastering is enabled. */ + pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, + pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | + PCI_COMMAND_MASTER_ENABLE); + + /* + * Map and establish our interrupt. + */ + if (pci_intr_map(pa, &ih)) { + printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname); + return; + } + intrstr = pci_intr_string(pa->pa_pc, ih); + psc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_NET, sf_intr, sc, + self->dv_xname); + if (psc->sc_ih == NULL) { + printf("%s: unable to establish interrupt", + sc->sc_dev.dv_xname); + if (intrstr != NULL) + printf(" at %s", intrstr); + return; + } + printf(": %s", intrstr); + + /* + * Finish off the attach. + */ + sf_attach(sc); +} diff --git a/sys/dev/pci/if_sfreg.h b/sys/dev/pci/if_sfreg.h deleted file mode 100644 index 889d29fc4a9..00000000000 --- a/sys/dev/pci/if_sfreg.h +++ /dev/null @@ -1,1057 +0,0 @@ -/* $OpenBSD: if_sfreg.h,v 1.9 2005/12/17 07:31:27 miod Exp $ */ -/* - * Copyright (c) 1997, 1998, 1999 - * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Bill Paul. - * 4. Neither the name of the author nor the names of any co-contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - * - * $FreeBSD: src/sys/pci/if_sfreg.h,v 1.6 1999/12/05 20:02:45 wpaul Exp $ - */ - -/* - * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K - * register space. These registers can be accessed in the following way: - * - PCI config registers are always accessible through PCI config space - * - Full 512K space mapped into memory using PCI memory mapped access - * - 256-byte I/O space mapped through PCI I/O access - * - Full 512K space mapped through indirect I/O using PCI I/O access - * It's possible to use either memory mapped mode or I/O mode to access - * the registers, but memory mapped is usually the easiest. All registers - * are 32 bits wide and must be accessed using 32-bit operations. - */ - -/* - * Adaptec PCI vendor ID. - */ -#define AD_VENDORID 0x9004 - -/* - * AIC-6915 PCI device ID. - */ -#define AD_DEVICEID_STARFIRE 0x6915 - -/* - * AIC-6915 subsystem IDs. Adaptec uses the subsystem ID to identify - * the exact kind of NIC on which the ASIC is mounted. Currently there - * are six different variations. Note: the Adaptec manual lists code 0x28 - * for two different NICs: the 62044 and the 69011/TX. This is a typo: - * the code for the 62044 is really 0x18. - */ -#define AD_SUBSYSID_62011_REV0 0x0008 /* single port 10/100baseTX 64-bit */ -#define AD_SUBSYSID_62011_REV1 0x0009 /* single port 10/100baseTX 64-bit */ -#define AD_SUBSYSID_62022 0x0010 /* dual port 10/100baseTX 64-bit */ -#define AD_SUBSYSID_62044 0x0018 /* quad port 10/100baseTX 64-bit */ -#define AD_SUBSYSID_62020 0x0020 /* single port 10/100baseFX 64-bit */ -#define AD_SUBSYSID_69011 0x0028 /* single port 10/100baseTX 32-bit */ - -/* - * Starfire internal register space map. The entire register space - * is available using PCI memory mapped mode. The SF_RMAP_INTREG - * space is available using PCI I/O mode. The entire space can be - * accessed using indirect I/O using the indirect I/O addr and - * indirect I/O data registers located within the SF_RMAP_INTREG space. - */ -#define SF_RMAP_ROMADDR_BASE 0x00000 /* Expansion ROM space */ -#define SF_RMAP_ROMADDR_MAX 0x3FFFF - -#define SF_RMAP_EXGPIO_BASE 0x40000 /* External general purpose regs */ -#define SF_RMAP_EXGPIO_MAX 0x3FFFF - -#define SF_RMAP_INTREG_BASE 0x50000 /* Internal functional registers */ -#define SF_RMAP_INTREG_MAX 0x500FF -#define SF_RMAP_GENREG_BASE 0x50100 /* General purpose registers */ -#define SF_RMAP_GENREG_MAX 0x5FFFF - -#define SF_RMAP_FIFO_BASE 0x60000 -#define SF_RMAP_FIFO_MAX 0x6FFFF - -#define SF_RMAP_STS_BASE 0x70000 -#define SF_RMAP_STS_MAX 0x70083 - -#define SF_RMAP_RSVD_BASE 0x70084 -#define SF_RMAP_RSVD_MAX 0x7FFFF - -/* - * PCI config header registers, 0x0000 to 0x003F - */ -#define SF_PCI_VENDOR_ID 0x0000 -#define SF_PCI_DEVICE_ID 0x0002 -#define SF_PCI_COMMAND 0x0004 -#define SF_PCI_STATUS 0x0006 -#define SF_PCI_REVID 0x0008 -#define SF_PCI_CLASSCODE 0x0009 -#define SF_PCI_CACHELEN 0x000C -#define SF_PCI_LATENCY_TIMER 0x000D -#define SF_PCI_HEADER_TYPE 0x000E -#define SF_PCI_LOMEM 0x0010 -#define SF_PCI_LOIO 0x0014 -#define SF_PCI_SUBVEN_ID 0x002C -#define SF_PCI_SYBSYS_ID 0x002E -#define SF_PCI_BIOSROM 0x0030 -#define SF_PCI_INTLINE 0x003C -#define SF_PCI_INTPIN 0x003D -#define SF_PCI_MINGNT 0x003E -#define SF_PCI_MINLAT 0x003F - -/* - * PCI registers, 0x0040 to 0x006F - */ -#define SF_PCI_DEVCFG 0x0040 -#define SF_BACCTL 0x0044 -#define SF_PCI_MON1 0x0048 -#define SF_PCI_MON2 0x004C -#define SF_PCI_CAPID 0x0050 /* 8 bits */ -#define SF_PCI_NEXTPTR 0x0051 /* 8 bits */ -#define SF_PCI_PWRMGMTCAP 0x0052 /* 16 bits */ -#define SF_PCI_PWRMGMTCTRL 0x0054 /* 16 bits */ -#define SF_PCI_PME_EVENT 0x0058 -#define SF_PCI_EECTL 0x0060 -#define SF_PCI_COMPLIANCE 0x0064 -#define SF_INDIRECTIO_ADDR 0x0068 -#define SF_INDIRECTIO_DATA 0x006C - -#define SF_PCIDEVCFG_RESET 0x00000001 -#define SF_PCIDEVCFG_FORCE64 0x00000002 -#define SF_PCIDEVCFG_SYSTEM64 0x00000004 -#define SF_PCIDEVCFG_RSVD0 0x00000008 -#define SF_PCIDEVCFG_INCR_INB 0x00000010 -#define SF_PCIDEVCFG_ABTONPERR 0x00000020 -#define SF_PCIDEVCFG_STPONPERR 0x00000040 -#define SF_PCIDEVCFG_MR_ENB 0x00000080 -#define SF_PCIDEVCFG_FIFOTHR 0x00000F00 -#define SF_PCIDEVCFG_STPONCA 0x00001000 -#define SF_PCIDEVCFG_PCIMEN 0x00002000 /* enable PCI bus master */ -#define SF_PCIDEVCFG_LATSTP 0x00004000 -#define SF_PCIDEVCFG_BYTE_ENB 0x00008000 -#define SF_PCIDEVCFG_EECSWIDTH 0x00070000 -#define SF_PCIDEVCFG_STPMWCA 0x00080000 -#define SF_PCIDEVCFG_REGCSWIDTH 0x00700000 -#define SF_PCIDEVCFG_INTR_ENB 0x00800000 -#define SF_PCIDEVCFG_DPR_ENB 0x01000000 -#define SF_PCIDEVCFG_RSVD1 0x02000000 -#define SF_PCIDEVCFG_RSVD2 0x04000000 -#define SF_PCIDEVCFG_STA_ENB 0x08000000 -#define SF_PCIDEVCFG_RTA_ENB 0x10000000 -#define SF_PCIDEVCFG_RMA_ENB 0x20000000 -#define SF_PCIDEVCFG_SSE_ENB 0x40000000 -#define SF_PCIDEVCFG_DPE_ENB 0x80000000 - -#define SF_BACCTL_BACDMA_ENB 0x00000001 -#define SF_BACCTL_PREFER_RXDMA 0x00000002 -#define SF_BACCTL_PREFER_TXDMA 0x00000004 -#define SF_BACCTL_SINGLE_DMA 0x00000008 -#define SF_BACCTL_SWAPMODE_DATA 0x00000030 -#define SF_BACCTL_SWAPMODE_DESC 0x000000C0 - -#define SF_SWAPMODE_LE 0x00000000 -#define SF_SWAPMODE_BE 0x00000010 - -#define SF_PSTATE_MASK 0x0003 -#define SF_PSTATE_D0 0x0000 -#define SF_PSTATE_D1 0x0001 -#define SF_PSTATE_D2 0x0002 -#define SF_PSTATE_D3 0x0003 -#define SF_PME_EN 0x0010 -#define SF_PME_STATUS 0x8000 - - -/* - * Ethernet registers 0x0070 to 0x00FF - */ -#define SF_GEN_ETH_CTL 0x0070 -#define SF_TIMER_CTL 0x0074 -#define SF_CURTIME 0x0078 -#define SF_ISR 0x0080 -#define SF_ISR_SHADOW 0x0084 -#define SF_IMR 0x0088 -#define SF_GPIO 0x008C -#define SF_TXDQ_CTL 0x0090 -#define SF_TXDQ_ADDR_HIPRIO 0x0094 -#define SF_TXDQ_ADDR_LOPRIO 0x0098 -#define SF_TXDQ_ADDR_HIADDR 0x009C -#define SF_TXDQ_PRODIDX 0x00A0 -#define SF_TXDQ_CONSIDX 0x00A4 -#define SF_TXDMA_STS1 0x00A8 -#define SF_TXDMA_STS2 0x00AC -#define SF_TX_FRAMCTL 0x00B0 -#define SF_TXCQ_ADDR_HI 0x00B4 -#define SF_TXCQ_CTL 0x00B8 -#define SF_RXCQ_CTL_1 0x00BC -#define SF_RXCQ_CTL_2 0x00C0 -#define SF_CQ_CONSIDX 0x00C4 -#define SF_CQ_PRODIDX 0x00C8 -#define SF_CQ_RXQ2 0x00CC -#define SF_RXDMA_CTL 0x00D0 -#define SF_RXDQ_CTL_1 0x00D4 -#define SF_RXDQ_CTL_2 0x00D8 -#define SF_RXDQ_ADDR_HIADDR 0x00DC -#define SF_RXDQ_ADDR_Q1 0x00E0 -#define SF_RXDQ_ADDR_Q2 0x00E4 -#define SF_RXDQ_PTR_Q1 0x00E8 -#define SF_RXDQ_PTR_Q2 0x00EC -#define SF_RXDMA_STS 0x00F0 -#define SF_RXFILT 0x00F4 -#define SF_RX_FRAMETEST_OUT 0x00F8 - -/* Ethernet control register */ -#define SF_ETHCTL_RX_ENB 0x00000001 -#define SF_ETHCTL_TX_ENB 0x00000002 -#define SF_ETHCTL_RXDMA_ENB 0x00000004 -#define SF_ETHCTL_TXDMA_ENB 0x00000008 -#define SF_ETHCTL_RXGFP_ENB 0x00000010 -#define SF_ETHCTL_TXGFP_ENB 0x00000020 -#define SF_ETHCTL_SOFTINTR 0x00000800 - -/* Timer control register */ -#define SF_TIMER_IMASK_INTERVAL 0x0000001F -#define SF_TIMER_IMASK_MODE 0x00000060 -#define SF_TIMER_SMALLFRAME_BYP 0x00000100 -#define SF_TIMER_SMALLRX_FRAME 0x00000600 -#define SF_TIMER_TIMES_TEN 0x00000800 -#define SF_TIMER_RXHIPRIO_BYP 0x00001000 -#define SF_TIMER_TX_DMADONE_DLY 0x00002000 -#define SF_TIMER_TX_QDONE_DLY 0x00004000 -#define SF_TIMER_TX_FRDONE_DLY 0x00008000 -#define SF_TIMER_GENTIMER 0x00FF0000 -#define SF_TIMER_ONESHOT 0x01000000 -#define SF_TIMER_GENTIMER_RES 0x02000000 -#define SF_TIMER_TIMEST_RES 0x04000000 -#define SF_TIMER_RXQ2DONE_DLY 0x10000000 -#define SF_TIMER_EARLYRX2_DLY 0x20000000 -#define SF_TIMER_RXQ1DONE_DLY 0x40000000 -#define SF_TIMER_EARLYRX1_DLY 0x80000000 - -/* Interrupt status register */ -#define SF_ISR_PCIINT_ASSERTED 0x00000001 -#define SF_ISR_GFP_TX 0x00000002 -#define SF_ISR_GFP_RX 0x00000004 -#define SF_ISR_TX_BADID_HIPRIO 0x00000008 -#define SF_ISR_TX_BADID_LOPRIO 0x00000010 -#define SF_ISR_NO_TX_CSUM 0x00000020 -#define SF_ISR_RXDQ2_NOBUFS 0x00000040 -#define SF_ISR_RXGFP_NORESP 0x00000080 -#define SF_ISR_RXDQ1_DMADONE 0x00000100 -#define SF_ISR_RXDQ2_DMADONE 0x00000200 -#define SF_ISR_RXDQ1_EARLY 0x00000400 -#define SF_ISR_RXDQ2_EARLY 0x00000800 -#define SF_ISR_TX_QUEUEDONE 0x00001000 -#define SF_ISR_TX_DMADONE 0x00002000 -#define SF_ISR_TX_TXDONE 0x00004000 -#define SF_ISR_NORMALINTR 0x00008000 -#define SF_ISR_RXDQ1_NOBUFS 0x00010000 -#define SF_ISR_RXCQ2_NOBUFS 0x00020000 -#define SF_ISR_TX_LOFIFO 0x00040000 -#define SF_ISR_DMAERR 0x00080000 -#define SF_ISR_PCIINT 0x00100000 -#define SF_ISR_TXCQ_NOBUFS 0x00200000 -#define SF_ISR_RXCQ1_NOBUFS 0x00400000 -#define SF_ISR_SOFTINTR 0x00800000 -#define SF_ISR_GENTIMER 0x01000000 -#define SF_ISR_ABNORMALINTR 0x02000000 -#define SF_ISR_RSVD0 0x04000000 -#define SF_ISR_STATSOFLOW 0x08000000 -#define SF_ISR_GPIO 0xF0000000 - -/* - * Shadow interrupt status register. Unlike the normal IRQ register, - * reading bits here does not automatically cause them to reset. - */ -#define SF_SISR_PCIINT_ASSERTED 0x00000001 -#define SF_SISR_GFP_TX 0x00000002 -#define SF_SISR_GFP_RX 0x00000004 -#define SF_SISR_TX_BADID_HIPRIO 0x00000008 -#define SF_SISR_TX_BADID_LOPRIO 0x00000010 -#define SF_SISR_NO_TX_CSUM 0x00000020 -#define SF_SISR_RXDQ2_NOBUFS 0x00000040 -#define SF_SISR_RXGFP_NORESP 0x00000080 -#define SF_SISR_RXDQ1_DMADONE 0x00000100 -#define SF_SISR_RXDQ2_DMADONE 0x00000200 -#define SF_SISR_RXDQ1_EARLY 0x00000400 -#define SF_SISR_RXDQ2_EARLY 0x00000800 -#define SF_SISR_TX_QUEUEDONE 0x00001000 -#define SF_SISR_TX_DMADONE 0x00002000 -#define SF_SISR_TX_TXDONE 0x00004000 -#define SF_SISR_NORMALINTR 0x00008000 -#define SF_SISR_RXDQ1_NOBUFS 0x00010000 -#define SF_SISR_RXCQ2_NOBUFS 0x00020000 -#define SF_SISR_TX_LOFIFO 0x00040000 -#define SF_SISR_DMAERR 0x00080000 -#define SF_SISR_PCIINT 0x00100000 -#define SF_SISR_TXCQ_NOBUFS 0x00200000 -#define SF_SISR_RXCQ1_NOBUFS 0x00400000 -#define SF_SISR_SOFTINTR 0x00800000 -#define SF_SISR_GENTIMER 0x01000000 -#define SF_SISR_ABNORMALINTR 0x02000000 -#define SF_SISR_RSVD0 0x04000000 -#define SF_SISR_STATSOFLOW 0x08000000 -#define SF_SISR_GPIO 0xF0000000 - -/* Interrupt mask register */ -#define SF_IMR_PCIINT_ASSERTED 0x00000001 -#define SF_IMR_GFP_TX 0x00000002 -#define SF_IMR_GFP_RX 0x00000004 -#define SF_IMR_TX_BADID_HIPRIO 0x00000008 -#define SF_IMR_TX_BADID_LOPRIO 0x00000010 -#define SF_IMR_NO_TX_CSUM 0x00000020 -#define SF_IMR_RXDQ2_NOBUFS 0x00000040 -#define SF_IMR_RXGFP_NORESP 0x00000080 -#define SF_IMR_RXDQ1_DMADONE 0x00000100 -#define SF_IMR_RXDQ2_DMADONE 0x00000200 -#define SF_IMR_RXDQ1_EARLY 0x00000400 -#define SF_IMR_RXDQ2_EARLY 0x00000800 -#define SF_IMR_TX_QUEUEDONE 0x00001000 -#define SF_IMR_TX_DMADONE 0x00002000 -#define SF_IMR_TX_TXDONE 0x00004000 -#define SF_IMR_NORMALINTR 0x00008000 -#define SF_IMR_RXDQ1_NOBUFS 0x00010000 -#define SF_IMR_RXCQ2_NOBUFS 0x00020000 -#define SF_IMR_TX_LOFIFO 0x00040000 -#define SF_IMR_DMAERR 0x00080000 -#define SF_IMR_PCIINT 0x00100000 -#define SF_IMR_TXCQ_NOBUFS 0x00200000 -#define SF_IMR_RXCQ1_NOBUFS 0x00400000 -#define SF_IMR_SOFTINTR 0x00800000 -#define SF_IMR_GENTIMER 0x01000000 -#define SF_IMR_ABNORMALINTR 0x02000000 -#define SF_IMR_RSVD0 0x04000000 -#define SF_IMR_STATSOFLOW 0x08000000 -#define SF_IMR_GPIO 0xF0000000 - -#define SF_INTRS \ - (SF_IMR_RXDQ2_NOBUFS|SF_IMR_RXDQ1_DMADONE|SF_IMR_RXDQ2_DMADONE| \ - SF_IMR_TX_TXDONE|SF_IMR_RXDQ1_NOBUFS|SF_IMR_RXDQ2_DMADONE| \ - SF_IMR_NORMALINTR|SF_IMR_ABNORMALINTR|SF_IMR_TXCQ_NOBUFS| \ - SF_IMR_RXCQ1_NOBUFS|SF_IMR_RXCQ2_NOBUFS|SF_IMR_STATSOFLOW| \ - SF_IMR_TX_LOFIFO) - -/* TX descriptor queue control registers */ -#define SF_TXDQCTL_DESCTYPE 0x00000007 -#define SF_TXDQCTL_NODMACMP 0x00000008 -#define SF_TXDQCTL_MINSPACE 0x00000070 -#define SF_TXDQCTL_64BITADDR 0x00000080 -#define SF_TXDQCTL_BURSTLEN 0x00003F00 -#define SF_TXDQCTL_SKIPLEN 0x001F0000 -#define SF_TXDQCTL_HIPRIOTHRESH 0xFF000000 - -#define SF_TXBUFDESC_TYPE0 0x00000000 -#define SF_TXBUFDESC_TYPE1 0x00000001 -#define SF_TXBUFDESC_TYPE2 0x00000002 -#define SF_TXBUFDESC_TYPE3 0x00000003 -#define SF_TXBUFDESC_TYPE4 0x00000004 - -#define SF_TXMINSPACE_UNLIMIT 0x00000000 -#define SF_TXMINSPACE_32BYTES 0x00000010 -#define SF_TXMINSPACE_64BYTES 0x00000020 -#define SF_TXMINSPACE_128BYTES 0x00000030 -#define SF_TXMINSPACE_256BYTES 0x00000040 - -#define SF_TXSKIPLEN_0BYTES 0x00000000 -#define SF_TXSKIPLEN_8BYTES 0x00010000 -#define SF_TXSKIPLEN_16BYTES 0x00020000 -#define SF_TXSKIPLEN_24BYTES 0x00030000 -#define SF_TXSKIPLEN_32BYTES 0x00040000 - -/* TX frame control register */ -#define SF_TXFRMCTL_TXTHRESH 0x000000FF -#define SF_TXFRMCTL_CPLAFTERTX 0x00000100 -#define SF_TXFRMCRL_DEBUG 0x0000FE00 -#define SF_TXFRMCTL_STATUS 0x01FF0000 -#define SF_TXFRMCTL_MAC_TXIF 0xFE000000 - -/* TX completion queue control register */ -#define SF_TXCQ_THRESH 0x0000000F -#define SF_TXCQ_COMMON 0x00000010 -#define SF_TXCQ_SIZE 0x00000020 -#define SF_TXCQ_WRITEENB 0x00000040 -#define SF_TXCQ_USE_64BIT 0x00000080 -#define SF_TXCQ_ADDR 0xFFFFFF00 - -/* RX completion queue control register */ -#define SF_RXCQ_THRESH 0x0000000F -#define SF_RXCQ_TYPE 0x00000030 -#define SF_RXCQ_WRITEENB 0x00000040 -#define SF_RXCQ_USE_64BIT 0x00000080 -#define SF_RXCQ_ADDR 0xFFFFFF00 - -#define SF_RXCQTYPE_0 0x00000000 -#define SF_RXCQTYPE_1 0x00000010 -#define SF_RXCQTYPE_2 0x00000020 -#define SF_RXCQTYPE_3 0x00000030 - -/* TX descriptor queue producer index register */ -#define SF_TXDQ_PRODIDX_LOPRIO 0x000007FF -#define SF_TXDQ_PRODIDX_HIPRIO 0x07FF0000 - -/* TX descriptor queue consumer index register */ -#define SF_TXDQ_CONSIDX_LOPRIO 0x000007FF -#define SF_TXDQ_CONSIDX_HIPRIO 0x07FF0000 - -/* Completion queue consumer index register */ -#define SF_CQ_CONSIDX_RXQ1 0x000003FF -#define SF_CQ_CONSIDX_RXTHRMODE 0x00008000 -#define SF_CQ_CONSIDX_TXQ 0x03FF0000 -#define SF_CQ_CONSIDX_TXTHRMODE 0x80000000 - -/* Completion queue producer index register */ -#define SF_CQ_PRODIDX_RXQ1 0x000003FF -#define SF_CQ_PRODIDX_TXQ 0x03FF0000 - -/* RX completion queue 2 consumer/producer index register */ -#define SF_CQ_RXQ2_CONSIDX 0x000003FF -#define SF_CQ_RXQ2_RXTHRMODE 0x00008000 -#define SF_CQ_RXQ2_PRODIDX 0x03FF0000 - -#define SF_CQ_RXTHRMODE_INT_ON 0x00008000 -#define SF_CQ_RXTHRMODE_INT_OFF 0x00000000 -#define SF_CQ_TXTHRMODE_INT_ON 0x80000000 -#define SF_CQ_TXTHRMODE_INT_OFF 0x00000000 - -#define SF_IDX_LO(x) ((x) & 0x000007FF) -#define SF_IDX_HI(x) (((x) >> 16) & 0x000007FF) - -/* RX DMA control register */ -#define SF_RXDMA_BURSTSIZE 0x0000007F -#define SF_RXDMA_FPTESTMODE 0x00000080 -#define SF_RXDMA_HIPRIOTHRESH 0x00000F00 -#define SF_RXDMA_RXEARLYTHRESH 0x0001F000 -#define SF_RXDMA_DMACRC 0x00040000 -#define SF_RXDMA_USEBKUPQUEUE 0x00080000 -#define SF_RXDMA_QUEUEMODE 0x00700000 -#define SF_RXDMA_RXCQ2_ON 0x00800000 -#define SF_RXDMA_CSUMMODE 0x03000000 -#define SF_RXDMA_DMAPAUSEPKTS 0x04000000 -#define SF_RXDMA_DMACTLPKTS 0x08000000 -#define SF_RXDMA_DMACRXERRPKTS 0x10000000 -#define SF_RXDMA_DMABADPKTS 0x20000000 -#define SF_RXDMA_DMARUNTS 0x40000000 -#define SF_RXDMA_REPORTBADPKTS 0x80000000 - -#define SF_RXDQMODE_Q1ONLY 0x00100000 -#define SF_RXDQMODE_Q2_ON_FP 0x00200000 -#define SF_RXDQMODE_Q2_ON_SHORT 0x00300000 -#define SF_RXDQMODE_Q2_ON_PRIO 0x00400000 -#define SF_RXDQMODE_SPLITHDR 0x00500000 - -#define SF_RXCSUMMODE_IGNORE 0x00000000 -#define SF_RXCSUMMODE_REJECT_BAD_TCP 0x01000000 -#define SF_RXCSUMMODE_REJECT_BAD_TCPUDP 0x02000000 -#define SF_RXCSUMMODE_RSVD 0x03000000 - -/* RX descriptor queue control registers */ -#define SF_RXDQCTL_MINDESCTHR 0x0000007F -#define SF_RXDQCTL_Q1_WE 0x00000080 -#define SF_RXDQCTL_DESCSPACE 0x00000700 -#define SF_RXDQCTL_64BITDADDR 0x00000800 -#define SF_RXDQCTL_64BITBADDR 0x00001000 -#define SF_RXDQCTL_VARIABLE 0x00002000 -#define SF_RXDQCTL_ENTRIES 0x00004000 -#define SF_RXDQCTL_PREFETCH 0x00008000 -#define SF_RXDQCTL_BUFLEN 0xFFFF0000 - -#define SF_DESCSPACE_4BYTES 0x00000000 -#define SF_DESCSPACE_8BYTES 0x00000100 -#define SF_DESCSPACE_16BYTES 0x00000200 -#define SF_DESCSPACE_32BYTES 0x00000300 -#define SF_DESCSPACE_64BYTES 0x00000400 -#define SF_DESCSPACE_128_BYTES 0x00000500 - -/* RX buffer consumer/producer index registers */ -#define SF_RXDQ_PRODIDX 0x000007FF -#define SF_RXDQ_CONSIDX 0x07FF0000 - -/* RX filter control register */ -#define SF_RXFILT_PROMISC 0x00000001 -#define SF_RXFILT_ALLMULTI 0x00000002 -#define SF_RXFILT_BROAD 0x00000004 -#define SF_RXFILT_HASHPRIO 0x00000008 -#define SF_RXFILT_HASHMODE 0x00000030 -#define SF_RXFILT_PERFMODE 0x000000C0 -#define SF_RXFILT_VLANMODE 0x00000300 -#define SF_RXFILT_WAKEMODE 0x00000C00 -#define SF_RXFILT_MULTI_NOBROAD 0x00001000 -#define SF_RXFILT_MIN_VLANPRIO 0x0000E000 -#define SF_RXFILT_PEFECTPRIO 0xFFFF0000 - -/* Hash filtering mode */ -#define SF_HASHMODE_OFF 0x00000000 -#define SF_HASHMODE_WITHVLAN 0x00000010 -#define SF_HASHMODE_ANYVLAN 0x00000020 -#define SF_HASHMODE_ANY 0x00000030 - -/* Perfect filtering mode */ -#define SF_PERFMODE_OFF 0x00000000 -#define SF_PERFMODE_NORMAL 0x00000040 -#define SF_PERFMODE_INVERSE 0x00000080 -#define SF_PERFMODE_VLAN 0x000000C0 - -/* VLAN mode */ -#define SF_VLANMODE_OFF 0x00000000 -#define SF_VLANMODE_NOSTRIP 0x00000100 -#define SF_VLANMODE_STRIP 0x00000200 -#define SF_VLANMODE_RSVD 0x00000300 - -/* Wakeup mode */ -#define SF_WAKEMODE_OFF 0x00000000 -#define SF_WAKEMODE_FILTER 0x00000400 -#define SF_WAKEMODE_FP 0x00000800 -#define SF_WAKEMODE_HIPRIO 0x00000C00 - -/* - * Extra PCI registers 0x0100 to 0x0FFF - */ -#define SF_PCI_TARGSTAT 0x0100 -#define SF_PCI_MASTSTAT1 0x0104 -#define SF_PCI_MASTSTAT2 0x0108 -#define SF_PCI_DMAHOSTADDR_LO 0x010C -#define SF_BAC_DMADIAG0 0x0110 -#define SF_BAC_DMADIAG1 0x0114 -#define SF_BAC_DMADIAG2 0x0118 -#define SF_BAC_DMADIAG3 0x011C -#define SF_PAR0 0x0120 -#define SF_PAR1 0x0124 -#define SF_PCICB_FUNCEVENT 0x0130 -#define SF_PCICB_FUNCEVENT_MASK 0x0134 -#define SF_PCICB_FUNCSTATE 0x0138 -#define SF_PCICB_FUNCFORCE 0x013C - -/* - * Serial EEPROM registers 0x1000 to 0x1FFF - * Presumeably the EEPROM is mapped into this 8K window. - */ -#define SF_EEADDR_BASE 0x1000 -#define SF_EEADDR_MAX 0x1FFF - -#define SF_EE_NODEADDR 14 - -/* - * MII registers registers 0x2000 to 0x3FFF - * There are 32 sets of 32 registers, one set for each possible - * PHY address. Each 32 bit register is split into a 16-bit data - * port and a couple of status bits. - */ - -#define SF_MIIADDR_BASE 0x2000 -#define SF_MIIADDR_MAX 0x3FFF -#define SF_MII_BLOCKS 32 - -#define SF_MII_DATAVALID 0x80000000 -#define SF_MII_BUSY 0x40000000 -#define SF_MII_DATAPORT 0x0000FFFF - -#define SF_PHY_REG(phy, reg) \ - (SF_MIIADDR_BASE + (phy * SF_MII_BLOCKS * sizeof(u_int32_t)) + \ - (reg * sizeof(u_int32_t))) - -/* - * Ethernet extra registers 0x4000 to 0x4FFF - */ -#define SF_TESTMODE 0x4000 -#define SF_RX_FRAMEPROC_CTL 0x4004 -#define SF_TX_FRAMEPROC_CTL 0x4008 - -/* - * MAC registers 0x5000 to 0x5FFF - */ -#define SF_MACCFG_1 0x5000 -#define SF_MACCFG_2 0x5004 -#define SF_BKTOBKIPG 0x5008 -#define SF_NONBKTOBKIPG 0x500C -#define SF_COLRETRY 0x5010 -#define SF_MAXLEN 0x5014 -#define SF_TXNIBBLECNT 0x5018 -#define SF_TXBYTECNT 0x501C -#define SF_RETXCNT 0x5020 -#define SF_RANDNUM 0x5024 -#define SF_RANDNUM_MASK 0x5028 -#define SF_TOTALTXCNT 0x5034 -#define SF_RXBYTECNT 0x5040 -#define SF_TXPAUSETIMER 0x5060 -#define SF_VLANTYPE 0x5064 -#define SF_MIISTATUS 0x5070 - -#define SF_MACCFG1_HUGEFRAMES 0x00000001 -#define SF_MACCFG1_FULLDUPLEX 0x00000002 -#define SF_MACCFG1_AUTOPAD 0x00000004 -#define SF_MACCFG1_HDJAM 0x00000008 -#define SF_MACCFG1_DELAYCRC 0x00000010 -#define SF_MACCFG1_NOBACKOFF 0x00000020 -#define SF_MACCFG1_LENGTHCHECK 0x00000040 -#define SF_MACCFG1_PUREPREAMBLE 0x00000080 -#define SF_MACCFG1_PASSALLRX 0x00000100 -#define SF_MACCFG1_PREAM_DETCNT 0x00000200 -#define SF_MACCFG1_RX_FLOWENB 0x00000400 -#define SF_MACCFG1_TX_FLOWENB 0x00000800 -#define SF_MACCFG1_TESTMODE 0x00003000 -#define SF_MACCFG1_MIILOOPBK 0x00004000 -#define SF_MACCFG1_SOFTRESET 0x00008000 - -/* - * These are the recommended IPG nibble counter settings - * specified in the Adaptec manual for full duplex and - * half duplex operation. - */ -#define SF_IPGT_FDX 0x15 -#define SF_IPGT_HDX 0x11 - -/* - * RX filter registers 0x6000 to 0x6FFF - */ -#define SF_RXFILT_PERFECT_BASE 0x6000 -#define SF_RXFILT_PERFECT_MAX 0x60FF -#define SF_RXFILT_PERFECT_SKIP 0x0010 -#define SF_RXFILT_PERFECT_CNT 0x0010 - -#define SF_RXFILT_HASH_BASE 0x6100 -#define SF_RXFILT_HASH_MAX 0x62FF -#define SF_RXFILT_HASH_SKIP 0x0010 -#define SF_RXFILT_HASH_CNT 0x001F -#define SF_RXFILT_HASH_ADDROFF 0x0000 -#define SF_RXFILT_HASH_PRIOOFF 0x0004 -#define SF_RXFILT_HASH_VLANOFF 0x0008 - -/* - * Statistics registers 0x7000 to 0x7FFF - */ -#define SF_STATS_BASE 0x7000 -#define SF_STATS_END 0x7FFF - -/* - * TX frame processor instruction space 0x8000 to 0x9FFF - */ - -/* - * RX frame processor instruction space 0xA000 to 0xBFFF - */ - -/* - * Ethernet FIFO access space 0xC000 to 0xDFFF - */ - -/* - * Reserved 0xE000 to 0xFFFF - */ - -/* - * Descriptor data structures. - */ - - -/* Receive descriptor formats. */ -#define SF_RX_MINSPACING 8 -#define SF_RX_DLIST_CNT 256 -#define SF_RX_CLIST_CNT 1024 -#define SF_RX_HOSTADDR(x) (((x) >> 2) & 0x3FFFFFFF) - -/* - * RX buffer descriptor type 0, 32-bit addressing. Note that we - * program the RX buffer queue control register(s) to allow a - * descriptor spacing of 16 bytes, which leaves room after each - * descriptor to store a pointer to the mbuf for each buffer. - */ -struct sf_rx_bufdesc_type0 { - u_int32_t sf_valid:1, - sf_end:1, - sf_addrlo:30; - u_int32_t sf_pad0; -#ifdef __i386__ - u_int32_t sf_pad1; -#endif - struct mbuf *sf_mbuf; -}; - -/* - * RX buffer descriptor type 0, 64-bit addressing. - */ -struct sf_rx_bufdesc_type1 { - u_int32_t sf_valid:1, - sf_end:1, - sf_addrlo:30; - u_int32_t sf_addrhi; -#ifdef __i386__ - u_int32_t sf_pad; -#endif - struct mbuf *sf_mbuf; -}; - -/* - * RX completion descriptor, type 0 (short). - */ -struct sf_rx_cmpdesc_type0 { - u_int32_t sf_len:16, - sf_endidx:11, - sf_status1:3, - sf_id:2; -}; - -/* - * RX completion descriptor, type 1 (basic). Includes vlan ID - * if this is a vlan-addressed packet, plus extended status. - */ -struct sf_rx_cmpdesc_type1 { - u_int32_t sf_len:16, - sf_endidx:11, - sf_status1:3, - sf_id:2; - u_int16_t sf_status2; - u_int16_t sf_vlanid; -}; - -/* - * RX completion descriptor, type 2 (checksum). Includes partial TCP/IP - * checksum instead of vlan tag, plus extended status. - */ -struct sf_rx_cmpdesc_type2 { - u_int32_t sf_len:16, - sf_endidx:11, - sf_status1:3, - sf_id:2; - u_int16_t sf_status2; - u_int16_t sf_cksum; -}; - -/* - * RX completion descriptor type 3 (full). Includes timestamp, partial - * TCP/IP checksum, vlan tag plus priority, two extended status fields. - */ -struct sf_rx_cmpdesc_type3 { - u_int32_t sf_len:16, - sf_endidx:11, - sf_status1:3, - sf_id:2; - u_int32_t sf_startidx:10, - sf_status3:6, - sf_status2:16; - u_int16_t sf_cksum; - u_int16_t sf_vlanid_prio; - u_int32_t sf_timestamp; -}; - -#define SF_RXSTAT1_QUEUE 0x1 -#define SF_RXSTAT1_FIFOFULL 0x2 -#define SF_RXSTAT1_OK 0x4 - - /* 0=unknown,5=unsupported */ -#define SF_RXSTAT2_FRAMETYPE 0x0007 /* 1=IPv4,2=IPv2,3=IPX,4=ICMP */ -#define SF_RXSTAT2_UDP 0x0008 -#define SF_RXSTAT2_TCP 0x0010 -#define SF_RXSTAT2_FRAG 0x0020 -#define SF_RXSTAT2_PCSUM_OK 0x0040 /* partial checksum ok */ -#define SF_RXSTAT2_CSUM_BAD 0x0080 /* TCP/IP checksum bad */ -#define SF_RXSTAT2_CSUM_OK 0x0100 /* TCP/IP checksum ok */ -#define SF_RXSTAT2_VLAN 0x0200 -#define SF_RXSTAT2_BADRXCODE 0x0400 -#define SF_RXSTAT2_DRIBBLE 0x0800 -#define SF_RXSTAT2_ISL_CRCERR 0x1000 -#define SF_RXSTAT2_CRCERR 0x2000 -#define SF_RXSTAT2_HASH 0x4000 -#define SF_RXSTAT2_PERFECT 0x8000 - -#define SF_RXSTAT3_TRAILER 0x01 -#define SF_RXSTAT3_HEADER 0x02 -#define SF_RXSTAT3_CONTROL 0x04 -#define SF_RXSTAT3_PAUSE 0x08 -#define SF_RXSTAT3_ISL 0x10 - -/* - * Transmit descriptor formats. - * Each transmit descriptor type allows for a skip field at the - * start of each structure. The size of the skip field can vary, - * however we always set it for 8 bytes, which is enough to hold - * a pointer (32 bits on x86, 64-bits on alpha) that we can use - * to hold the address of the head of the mbuf chain for the - * frame or fragment associated with the descriptor. This saves - * us from having to create a separate pointer array to hold - * the mbuf addresses. - */ -#define SF_TX_BUFDESC_ID 0xB -#define SF_MAXFRAGS 14 -#define SF_TX_MINSPACING 128 -#define SF_TX_DLIST_CNT 128 -#define SF_TX_DLIST_SIZE 16384 -#define SF_TX_SKIPLEN 1 -#define SF_TX_CLIST_CNT 1024 - -struct sf_frag { - u_int32_t sf_addr; - u_int16_t sf_fraglen; - u_int16_t sf_pktlen; -}; - -struct sf_frag_msdos { - u_int16_t sf_pktlen; - u_int16_t sf_fraglen; - u_int32_t sf_addr; -}; - -/* - * TX frame descriptor type 0, 32-bit addressing. One descriptor can - * be used to map multiple packet fragments. We use this format since - * BSD networking fragments packet data across mbuf chains. Note that - * the number of fragments can be variable depending on how the descriptor - * spacing is specified in the TX descriptor queue control register. - * We always use a spacing of 128 bytes, and a skipfield length of 8 - * bytes: this means 16 bytes for the descriptor, including the skipfield, - * with 121 bytes left for fragment maps. Each fragment requires 8 bytes, - * which allows for 14 fragments per descriptor. The total size of the - * transmit buffer queue is limited to 16384 bytes, so with a spacing of - * 128 bytes per descriptor, we have room for 128 descriptors in the queue. - */ -struct sf_tx_bufdesc_type0 { -#ifdef __i386__ - u_int32_t sf_pad; -#endif - struct mbuf *sf_mbuf; - u_int32_t sf_rsvd0:24, - sf_crcen:1, - sf_caltcp:1, - sf_end:1, - sf_intr:1, - sf_id:4; - u_int8_t sf_fragcnt; - u_int8_t sf_rsvd2; - u_int16_t sf_rsvd1; - struct sf_frag sf_frags[14]; -}; - -/* - * TX buffer descriptor type 1, 32-bit addressing. Each descriptor - * maps a single fragment. - */ -struct sf_tx_bufdesc_type1 { -#ifdef __i386__ - u_int32_t sf_pad; -#endif - struct mbuf *sf_mbuf; - u_int32_t sf_fraglen:16, - sf_fragcnt:8, - sf_crcen:1, - sf_caltcp:1, - sf_end:1, - sf_intr:1, - sf_id:4; - u_int32_t sf_addr; -}; - -/* - * TX buffer descriptor type 2, 64-bit addressing. Each descriptor - * maps a single fragment. - */ -struct sf_tx_bufdesc_type2 { -#ifdef __i386__ - u_int32_t sf_pad; -#endif - struct mbuf *sf_mbuf; - u_int32_t sf_fraglen:16, - sf_fragcnt:8, - sf_crcen:1, - sf_caltcp:1, - sf_end:1, - sf_intr:1, - sf_id:4; - u_int32_t sf_addrlo; - u_int32_t sf_addrhi; -}; - -/* TX buffer descriptor type 3 is not defined. */ - -/* - * TX frame descriptor type 4, 32-bit addressing. This is a special - * case of the type 0 descriptor, identical except that the fragment - * address and length fields are ordered differently. This is done - * to optimize copies in MS-DOS and OS/2 drivers. - */ -struct sf_tx_bufdesc_type4 { -#ifdef __i386__ - u_int32_t sf_pad; -#endif - struct mbuf *sf_mbuf; - u_int32_t sf_rsvd0:24, - sf_crcen:1, - sf_caltcp:1, - sf_end:1, - sf_intr:1, - sf_id:4; - u_int8_t sf_fragcnt; - u_int8_t sf_rsvd2; - u_int16_t sf_rsvd1; - struct sf_frag_msdos sf_frags[14]; -}; - -/* - * Transmit completion queue descriptor formats. - */ - -/* - * Transmit DMA completion descriptor, type 0. - */ -#define SF_TXCMPTYPE_DMA 0x4 -struct sf_tx_cmpdesc_type0 { - u_int32_t sf_index:15, - sf_priority:1, - sf_timestamp:13, - sf_type:3; -}; - -/* - * Transmit completion descriptor, type 1. - */ -#define SF_TXCMPTYPE_TX 0x5 -struct sf_tx_cmpdesc_type1 { - u_int32_t sf_index:15, - sf_priority:1, - sf_txstat:13, - sf_type:3; -}; - -#define SF_TXSTAT_CRCERR 0x0001 -#define SF_TXSTAT_LENCHECKERR 0x0002 -#define SF_TXSTAT_LENRANGEERR 0x0004 -#define SF_TXSTAT_TX_OK 0x0008 -#define SF_TXSTAT_TX_DEFERED 0x0010 -#define SF_TXSTAT_EXCESS_DEFER 0x0020 -#define SF_TXSTAT_EXCESS_COLL 0x0040 -#define SF_TXSTAT_LATE_COLL 0x0080 -#define SF_TXSTAT_TOOBIG 0x0100 -#define SF_TXSTAT_TX_UNDERRUN 0x0200 -#define SF_TXSTAT_CTLFRAME_OK 0x0400 -#define SF_TXSTAT_PAUSEFRAME_OK 0x0800 -#define SF_TXSTAT_PAUSED 0x1000 - -/* Statistics counters. */ -struct sf_stats { - u_int32_t sf_tx_frames; - u_int32_t sf_tx_single_colls; - u_int32_t sf_tx_multi_colls; - u_int32_t sf_tx_crcerrs; - u_int32_t sf_tx_bytes; - u_int32_t sf_tx_defered; - u_int32_t sf_tx_late_colls; - u_int32_t sf_tx_pause_frames; - u_int32_t sf_tx_control_frames; - u_int32_t sf_tx_excess_colls; - u_int32_t sf_tx_excess_defer; - u_int32_t sf_tx_mcast_frames; - u_int32_t sf_tx_bcast_frames; - u_int32_t sf_tx_frames_lost; - u_int32_t sf_rx_rx_frames; - u_int32_t sf_rx_crcerrs; - u_int32_t sf_rx_alignerrs; - u_int32_t sf_rx_bytes; - u_int32_t sf_rx_control_frames; - u_int32_t sf_rx_unsup_control_frames; - u_int32_t sf_rx_giants; - u_int32_t sf_rx_runts; - u_int32_t sf_rx_jabbererrs; - u_int32_t sf_rx_pkts_64; - u_int32_t sf_rx_pkts_65_127; - u_int32_t sf_rx_pkts_128_255; - u_int32_t sf_rx_pkts_256_511; - u_int32_t sf_rx_pkts_512_1023; - u_int32_t sf_rx_pkts_1024_1518; - u_int32_t sf_rx_frames_lost; - u_int16_t sf_tx_underruns; - u_int16_t sf_pad; -}; - -/* - * register space access macros - */ -#define CSR_WRITE_4(sc, reg, val) \ - bus_space_write_4(sc->sf_btag, sc->sf_bhandle, reg, val) - -#define CSR_READ_4(sc, reg) \ - bus_space_read_4(sc->sf_btag, sc->sf_bhandle, reg) - -#define CSR_READ_1(sc, reg) \ - bus_space_read_1(sc->sf_btag, sc->sf_bhandle, reg) - - -struct sf_type { - u_int16_t sf_vid; - u_int16_t sf_did; - char *sf_name; -}; - -#define SF_INC(x, y) (x) = (x + 1) % y - -/* - * Note: alignment is important here: each list must be aligned to - * a 256-byte boundary. It turns out that each ring is some multiple - * of 4K in length, so we can stack them all on top of each other - * and just worry about aligning the whole mess. There's one transmit - * buffer ring and two receive buffer rings: one RX ring is for small - * packets and the other is for large packets. Each buffer ring also - * has a companion completion queue. - */ -struct sf_list_data { - struct sf_tx_bufdesc_type0 sf_tx_dlist[SF_TX_DLIST_CNT]; - struct sf_tx_cmpdesc_type1 sf_tx_clist[SF_TX_CLIST_CNT]; - struct sf_rx_bufdesc_type0 sf_rx_dlist_big[SF_RX_DLIST_CNT]; -#ifdef notdef - /* - * Unfortunately, because the Starfire doesn't allow arbitrary - * byte alignment, we have to copy packets in the RX handler in - * order to align the payload correctly. This means that we - * don't gain anything by having separate large and small descriptor - * lists, so for now we don't bother with the small one. - */ - struct sf_rx_bufdesc_type0 sf_rx_dlist_small[SF_RX_DLIST_CNT]; -#endif - struct sf_rx_cmpdesc_type3 sf_rx_clist[SF_RX_CLIST_CNT]; -}; - -struct sf_softc { - struct device sc_dev; /* generic device structure */ - void *sc_ih; /* interrupt handler cookie */ - struct arpcom arpcom; /* interface info */ - struct ifmedia ifmedia; /* media info */ - struct timeout sc_stats_tmo; - mii_data_t sc_mii; /* mii bus */ - bus_space_handle_t sf_bhandle; /* bus space handle */ - bus_space_tag_t sf_btag; /* bus space tag */ - void *sf_intrhand; /* interrupt handler cookie */ - struct sf_type *sf_info; /* Starfire adapter info */ - struct sf_type *sf_pinfo; - u_int8_t sf_type; - u_int8_t sf_phy_addr; - u_int8_t sf_want_auto; - u_int8_t sf_autoneg; - u_int8_t sf_tx_pend; - struct sf_list_data *sf_ldata; - caddr_t sf_ldata_ptr; - int sf_tx_cnt; - u_int8_t sf_link; - int sf_if_flags; -}; - -#define SF_TIMEOUT 1000 - -#ifdef __alpha__ -#undef vtophys -#define vtophys(va) alpha_XXX_dmamap((vaddr_t)va) -#endif |