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* Fix IA32_EPT_VPID_CAP_XO_TRANSLATIONS specificationdv2021-03-291-2/+2
* spellingjsg2021-03-112-4/+4
* stop showing amd l3 cache informationjsg2020-12-221-9/+2
* Delete unused #defines: T_USER hasn't been used since July 2018guenther2020-11-131-8/+1
* Simplify interrupt entry stubs to not push around bogus trapno+errguenther2020-11-121-29/+30
* Give sizes and types to more functions and objects.guenther2020-11-091-5/+3
* Restore abstraction of register saving into macros in frameasm.hguenther2020-11-021-8/+63
* Use "memory" on inline fence instructions to suggest to the compilerjsg2020-10-281-4/+4
* Adding IOMMU support for AMD Vi and Intel VTD (disabled)jordan2020-10-271-2/+3
* Save and restore the MXCSR register and the FPU control word such thatkettenis2020-10-211-1/+2
* add an ipi for wbinvd and a linux style wbinvd_on_all_cpus() functionjsg2020-09-132-3/+15
* add SRBDS cpuid bitsjsg2020-09-131-1/+4
* Clean up the amd64 userland timecounter implementation a bit:kettenis2020-07-081-3/+2
* Add support for timeconting in userland.pirofti2020-07-061-0/+24
* Use an LFENCE instruction everywhere where we use RDTSC when we arekettenis2020-07-031-1/+10
* Remove obsolete <machine/stdarg.h> header. Nowadays the varargvisa2020-06-301-58/+0
* pci_intr_establish_cpu() for establishing an interrupt no a specific cpu.dlg2020-06-172-4/+7
* let the random subsystem read the tsc for event "timestamps".dlg2020-06-031-2/+10
* introduce "cpu_rnd_messybits" for use instead of nanotime in dev/rnd.c.dlg2020-05-311-1/+3
* Kill biospoll/pctrpoll defines and use `seltrue' directly in cdev_*_init().mpi2020-05-131-3/+1
* Use the same inittodr()/resettodr() implementation as on arm64/armv7/sparc64kettenis2020-04-281-1/+2
* Remove unused protoype.kettenis2020-04-151-2/+1
* vmm(4): add IOCTL handler to sets the access protections of the eptpd2020-04-082-7/+29
* vmm(4): handle cr0 writes more correctly for vmxpd2020-04-081-1/+3
* Take a swing at blocking Load-Value-Injection attacks against theguenther2020-03-111-9/+4
* oops some snapshot tests fell inderaadt2020-02-281-4/+9
* syncderaadt2020-02-281-9/+4
* controler -> controllerjsg2020-02-201-3/+3
* Machines have started to appear that have the framebuffer at an address > 4GB.kettenis2020-01-241-1/+5
* Remove trailing whitespace, no code change.mlarkin2020-01-221-3/+3
* Machines with many CPUs and long feature lists fill up the dmesg(8)bluhm2019-12-231-2/+2
* Disable TSX when MSR_ARCH_CAPABILITIES sets TSX_CTRL.jsg2019-12-202-4/+9
* Convert boolean_t/TRUE/FALSE to int/1/0 for coherency with the rest ofmpi2019-12-191-3/+3
* Fix size of reserved bytes section in xsave header.mortimer2019-11-291-2/+2
* Pass the EFI memory map to the kernel.kettenis2019-11-291-1/+8
* Convert db_addr_t -> vaddr_t but leave the typedef for now.mpi2019-11-071-2/+2
* Remove rdtsc macro.pirofti2019-08-261-8/+1
* Add TSC synchronization for multiprocessor machines.pirofti2019-08-092-2/+9
* Mitigate CVE-2019-1125: block speculation past conditional jump to mis-skipguenther2019-08-072-5/+21
* Add codepatch_jmp(), like codepath_call() but inserting a jmp instead of a call.guenther2019-08-071-2/+3
* Fix a typo I noticed reviewing the smbios code cleanup diff.kmos2019-08-041-2/+2
* Cleanup the bios(4)/smbios(4) code a bit. Fix some KNF issues, reducekettenis2019-08-042-132/+146
* emove duplicate definitions of LAPIC_ID_MASK and LAPIC_ID_SHIFT.kevlo2019-07-261-3/+1
* vmm/vmd: Fix migration with pvclockpd2019-07-171-1/+19
* Delete obsolete bits in a comment: mcontext is gone and struct reg is noguenther2019-07-141-3/+1
* Write back and invalidate caches before updating CPU microcode,bluhm2019-06-281-2/+2
* Implement suspend/resume support for MSI-X interrupts. Loosely based onkettenis2019-06-251-1/+8
* Add TSC_ADJUST CPUID flag.kettenis2019-06-141-1/+2
* Remove a 15 year old XXX commentmlarkin2019-05-281-2/+1
* Oops, forgot to include a copyright year when originally addedguenther2019-05-171-2/+2
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