wireguard-openbsd - WireGuard implementation for the OpenBSD kernel

	Commit message (Collapse)	Author	Age	Files	Lines
*	Let the armv7 bus_dma layer and simplebus(4) implementation deal with	kettenis	2020-04-29	1	-3/+2
\| \| \| \| \| \| \| \| \| \| \|	DMA remapping in the same way as arm64. This relies on the dma-ranges property in the device tree and allows us to get rid of the hack for the Raspberry Pi in the dwctwo(4) driver. Note that this does not include the hack in simplebus(4) that we have on arm64 since firmware that has the dma-ranges is in widespread use now. ok patrick@
*	Rework mainbus and implement simplebus to be able to span a tree-like	patrick	2016-05-02	1	-2/+2
\| \| \| \| \| \| \|	topology based on device tree information. Introduce a common attach args structure to be used for all fdt-capable bus devices. ok jsg@ kettenis@
*	Fix match function so that the cortex bus only attaches if the attach	patrick	2016-04-08	1	-2/+8
\| \| \| \| \| \|	args are actually looking for the cortex bus. ok kettenis@
*	add some more cortex A ids	jsg	2015-05-29	1	-2/+3
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*	The Cortex bus should be useful for Cortex-A7, too.	patrick	2013-08-06	1	-2/+3
\| \| \| \|	ok rapha@ jsg@
*	Add a cortex bus which represents the ARM MPCore Complex.	patrick	2013-05-01	1	-0/+158
	It will attach only to ARM Cortex A9 and A15 SoCs. The generic interrupt controller and timer will attach to this bus, later a secondary cache controller can be added. The base address for those controllers are figured out using the periphbase register. ok bmercer@