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* Bump MAXTSIZ to 256MB on i386.kurt2021-03-161-2/+2
| | | | okay deraadt@
* spellingjsg2021-03-117-14/+14
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* Geode CPU does not support SSE, so MXCSR does not exists there. Asbluhm2020-12-131-3/+2
| | | | | | | | our i386 compiler does not generate SSE instructions by default, it is not strictly necessary to save MXCSR content between setjmp(3) and longjmp(3). We do not want to end supporting such old processors now. Remove the stmxcsr and ldmxcsr instructions from libc. reported by Johan Huldtgren; OK jsg@ kettenis@
* Introduce constants to access the setjmp(3) jmp_buf fields frombluhm2020-12-061-2/+13
| | | | | | | i386 libc. The assembler code is more readable than with magic numbers. This brings i386 in line with amd64. No change in object file. OK kettenis@
* the legacy need_resched macro to access per-cpu value is no longer neededderaadt2020-09-241-3/+1
| | | | ok kettenis
* When operating in NX mode, GUCODE_SEL can cover the entire userlandderaadt2020-09-241-1/+2
| | | | | | | | | address space permanently, and the line-in-the-sand manipulation T_PROTFLT|T_USER fixup handling can be skipped. This change was written to side-step the segment-descriptor mismanagement issues, commited recently for the "go on i386" tested by sthen ok kettenis guenther
* Make sure we fetch the CS limit of the CPU the trap happened on. It iskettenis2020-09-242-3/+5
| | | | | | | | | | | | | possible to switch CPUs when handling a trap since we need to lock the vm_map of the process. In that case the CS limit would be wrong an we incorrectly decide that there has been an execute privilige violation. Also make sure we only modify the variables that keep track of the CS limit and segment descriptor while holding the kernel lock. Fixes builds of go ports on i386. tested by sthen@ ok deraadt@
* shuffle "extern int cpu_pae" into cpu.h, as the number of users will soonderaadt2020-09-231-1/+2
| | | | | increase. ok kettenis
* add an ipi for wbinvd and a linux style wbinvd_on_all_cpus() functionjsg2020-09-132-4/+16
| | | | ok kettenis@ deraadt@
* add SRBDS cpuid bitsjsg2020-09-131-1/+6
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* Add support for timeconting in userland.pirofti2020-07-061-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | This diff exposes parts of clock_gettime(2) and gettimeofday(2) to userland via libc eliberating processes from the need for a context switch everytime they want to count the passage of time. If a timecounter clock can be exposed to userland than it needs to set its tc_user member to a non-zero value. Tested with one or multiple counters per architecture. The timing data is shared through a pointer found in the new ELF auxiliary vector AUX_openbsd_timekeep containing timehands information that is frequently updated by the kernel. Timing differences between the last kernel update and the current time are adjusted in userland by the tc_get_timecount() function inside the MD usertc.c file. This permits a much more responsive environment, quite visible in browsers, office programs and gaming (apparently one is are able to fly in Minecraft now). Tested by robert@, sthen@, naddy@, kmos@, phessler@, and many others! OK from at least kettenis@, cheloha@, naddy@, sthen@
* Remove obsolete <machine/stdarg.h> header. Nowadays the varargvisa2020-06-301-54/+0
| | | | | | | | functionality is provided by <sys/stdarg.h> using compiler builtins. Tested in a ports bulk build on amd64 by naddy@ OK naddy@ mpi@
* introduce "cpu_rnd_messybits" for use instead of nanotime in dev/rnd.c.dlg2020-05-311-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | rnd.c uses nanotime to get access to some bits that change quickly between events that it can mix into the entropy pool. it doesn't use nanotime to get a monotonically increasing set or ordered and accurate timestamps, it just wants something with bits that change. there's been discussions for years about letting rnd use a clock that's super fast to read, but not necessarily accurate, but it wasn't until recently that i figured out it wasn't interested in time at all, so things like keeping a fast clock coherent between cpu cores or correct according to ntp is unecessary. this means we can just let rnd read the cycle counters on cpus and things will be fine. cpus with cycle counters that vary in their speed and arent kept consistent between cores may even be desirable in this context. so this is the first step in converting rnd.c to reading cycle counter. it copies the nanotime backend to each arch, and they can replace it with something MD as a second step later on. djm@ suggested rnd_messybytes, but we landed on cpu_rnd_messybits. thanks to visa for his eyes. ok deraadt@ visa@ deraadt@ says he will help handle any MD fallout that occurs.
* Retire <machine/varargs.h>.visa2020-05-271-58/+0
| | | | | | Nothing uses the header anymore. OK deraadt@ mpi@
* Kill unused cdev_pc_init().mpi2020-05-251-10/+1
| | | | ok kettenis@, visa@
* Kill biospoll/pctrpoll defines and use `seltrue' directly in cdev_*_init().mpi2020-05-131-3/+1
| | | | | | | While here use the kqfilter equivalent to `seltrue' to ensure both interfaces are coherent. ok visa@
* Use the same inittodr()/resettodr() implementation as onkettenis2020-04-291-2/+2
| | | | | | | | amd64/arm64/armv7/sparc64 and move it to the end of machdep.c. Rework the actual implementation for the MC14818 compatible RTC into something that can be used as a todr_handle just like on amd64. ok sthen@
* controler -> controllerjsg2020-02-201-3/+3
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* Disable TSX when MSR_ARCH_CAPABILITIES sets TSX_CTRL.jsg2019-12-202-2/+10
| | | | | | | | | | | | | | | | | | | | Even with the latest microcode this is not set on all CPUs with TSX, but is set on CPUs which don't need MDS mitigations. MDS mitigations also mitigate TSX Asynchronous Abort (TAA) but aren't done if the CPU claims to not be affected by MDS (MDS_NO). According to "Deep Dive: Intel Transactional Synchronization Extensions (Intel TSX) Asynchronous Abort" CPUs requiring additional mitigations for this are: 06-8e-0c Whiskey Lake (ULT refresh) 06-55-0{6,7} 2nd Gen Xeon Scalable Processors based on Cascade Lake 06-9e-0d Coffee Lake R Currently TSX is disabled unconditionally when possible even if TAA_NO is set. We don't currently do MDS mitigations on i386. Attempt to disable TSX regardless to match amd64.
* Convert boolean_t/TRUE/FALSE to int/1/0 for coherency with the rest ofmpi2019-12-191-18/+18
| | | | | | the kernel. ok mlarkin@, visa@
* Remove kernel VM86 support.mpi2019-12-081-43/+0
| | | | | | | Its last consumer is now gone and it has certainly not been used since the introduction of PAE back in 2015. ok kettenis@, jsg@
* Convert db_addr_t -> vaddr_t but leave the typedef for now.mpi2019-11-071-2/+2
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* Fix a typo I noticed reviewing the smbios code cleanup diff.kmos2019-08-041-2/+2
| | | | | | (stirng -> string) ok kettenis@ who pointed out I should fix the new arm64 smbiosvar.h too
* Cleanup the bios(4)/smbios(4) code a bit. Fix some KNF issues, reducekettenis2019-08-042-142/+156
| | | | | | | differences between the i386 and amd64 versions of the code and switch to using the standard C integer exact width integer types. ok deraadt@
* emove duplicate definitions of LAPIC_ID_MASK and LAPIC_ID_SHIFT.kevlo2019-07-261-3/+1
| | | | "yes please" guenther@
* Write back and invalidate caches before updating CPU microcode,bluhm2019-06-281-2/+2
| | | | | | like Intel does in their patches on githup. Also add a compiler level memory barrier to the wbinvd instruction like Linux does. OK mlarkin@ guenther@ kettenis@
* Add TSC_ADJUST CPUID flag.kettenis2019-06-141-1/+2
| | | | ok deraadt@, mlarkin@
* change marks[] array to uint64_t, so the code can track full 64-bitderaadt2019-04-101-2/+2
| | | | | details from the ELF header instead of faking it. Proposal from mlarkin, tested on most architectures already
* Use the debugger mutex for `ddb_mp_mutex'. This should prevent a racevisa2019-03-231-2/+2
| | | | | | | | | | that could leave `ddb_mp_mutex' locked if one CPU incremented `db_active' while another CPU was in the critical section. When the race hit, the debugger was unable to resume execution or switch between CPUs. Race analyzed by patrick@ OK mpi@ patrick@
* flense more trailing whitespacephessler2019-01-221-4/+4
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* remove trailing whitespace in the Laptop Package part of the license text.phessler2019-01-221-4/+4
| | | | no words or punctation were modified.
* delete vmm(4) in i386pd2019-01-187-1332/+8
| | | | | | | | | | | | We will still be able to run i386 guests on amd64 vmm. Reasons to delete i386 vmm: - Been broken for a while, almost no one complained. - Had been falling out of sync from amd64 while it worked. - If your machine has vmx, you most probably can run amd64, so why not run that? ok deraadt@ mlarkin@
* Include srp.h where struct cpu_info uses srp to avoid erroring out whenjsg2018-12-051-1/+2
| | | | | | | including cpu.h machine/intr.h etc without first including param.h when MULTIPROCESSOR is defined. ok visa@
* Unify the MD byteswapping code as much as possible across architectures.naddy2018-10-021-24/+25
| | | | | | | Use inline functions instead of GNU C statement expressions, and make them available to userland. With clues from guenther@. ok guenther@ kettenis@
* Add defines for amd microcode msrs which appear to be present since k8jsg2018-09-111-1/+3
| | | | though amd only provides public redistributable updates for >= family 10h.
* First pass in bringing i386 in sync with amd64. This does not yet work, but ispd2018-08-291-1/+43
| | | | | | being committed now so we can work on the rest in-tree. ok mlarkin@
* Define __HAVE_ACPI.kettenis2018-08-251-1/+3
| | | | ok deraadt@, krw@, jca@
* port the amd64 code for loading intel microcode on boot to i386jsg2018-08-233-3/+13
| | | | ok deraadt@ mlarkin@
* print rdtscp and xsave_ext cpuid bits on i386 as welljsg2018-08-211-1/+22
| | | | move printing of ecxfeatures bits to match amd64
* print sefflags_edx cpuid bits on i386 as welljsg2018-08-211-1/+2
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* Remove unused spllock().visa2018-08-201-2/+1
| | | | OK deraadt@ mpi@
* add cpuid and msr bits fromjsg2018-08-151-6/+21
| | | | | 'Deep Dive: CPUID Enumeration and Architectural MSRs' ok deraadt@
* Recognise 'Speculative Store Bypass Disable' support cpuid bit.jsg2018-08-081-1/+2
| | | | | Documented in 'Speculative Execution Side Channel Mitigations' revision 2.0.
* Use the MI interrupt enable/distable API instead of the MD one on i386 andkettenis2018-07-301-17/+3
| | | | | | remove the MD API. ok deraadt@
* Do the same for i386 as amd64:brynet2018-07-241-1/+2
| | | | | | | | | | Add "Mitigation G-2" per AMD's Whitepaper "Software Techniques for Managing Speculation on AMD Processors" By setting MSR C001_1029[1]=1, LFENCE becomes a dispatch serializing instruction. ok deraadt@
* unbreak i386 build, thanks to pd@ for noticing. Same diff as I committedmlarkin2018-07-121-6/+16
| | | | earlier for amd64
* Delete the VM86 kernel option and i386_vm86(3) API: it's requiredguenther2018-07-094-189/+3
| | | | | | | a custom kernel for over 20 years. testing mlarkin@ ok deraadt@ phessler@ jca@ matthieu@
* Add intr_enable() function, intended for MI use to amd64 and i386 and usekettenis2018-06-301-1/+7
| | | | | | this in the acpi(4) suspend/resume code paths. ok deraadt@
* Finish the last missing piece for the i386 meltdown fix:bluhm2018-06-224-26/+32
| | | | | | | - handle protection fault on iret properly - handle NMI - actually enable U-K in pmap_switch() from hshoexer@; input guenther@; OK mlarkin@ deraadt@
* Save and restore retguard area during hibernate unpack. This copies themlarkin2018-06-211-2/+2
| | | | | | | original retguard data to the piglet and bcopys it back in place immediately before resuming via the ACPI Sx trampoline. ok deraadt, guenther, tested by many.
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