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2021-03-16Bump MAXTSIZ to 256MB on i386.kurt1-2/+2
2021-03-11spellingjsg7-14/+14
2020-12-13Geode CPU does not support SSE, so MXCSR does not exists there. Asbluhm1-3/+2
2020-12-06Introduce constants to access the setjmp(3) jmp_buf fields frombluhm1-2/+13
2020-09-24the legacy need_resched macro to access per-cpu value is no longer neededderaadt1-3/+1
2020-09-24When operating in NX mode, GUCODE_SEL can cover the entire userlandderaadt1-1/+2
2020-09-24Make sure we fetch the CS limit of the CPU the trap happened on. It iskettenis2-3/+5
2020-09-23shuffle "extern int cpu_pae" into cpu.h, as the number of users will soonderaadt1-1/+2
2020-09-13add an ipi for wbinvd and a linux style wbinvd_on_all_cpus() functionjsg2-4/+16
2020-09-13add SRBDS cpuid bitsjsg1-1/+6
2020-07-06Add support for timeconting in userland.pirofti1-0/+23
2020-06-30Remove obsolete <machine/stdarg.h> header. Nowadays the varargvisa1-54/+0
2020-05-31introduce "cpu_rnd_messybits" for use instead of nanotime in dev/rnd.c.dlg1-1/+3
2020-05-27Retire <machine/varargs.h>.visa1-58/+0
2020-05-25Kill unused cdev_pc_init().mpi1-10/+1
2020-05-13Kill biospoll/pctrpoll defines and use `seltrue' directly in cdev_*_init().mpi1-3/+1
2020-04-29Use the same inittodr()/resettodr() implementation as onkettenis1-2/+2
2020-02-20controler -> controllerjsg1-3/+3
2019-12-20Disable TSX when MSR_ARCH_CAPABILITIES sets TSX_CTRL.jsg2-2/+10
2019-12-19Convert boolean_t/TRUE/FALSE to int/1/0 for coherency with the rest ofmpi1-18/+18
2019-12-08Remove kernel VM86 support.mpi1-43/+0
2019-11-07Convert db_addr_t -> vaddr_t but leave the typedef for now.mpi1-2/+2
2019-08-04Fix a typo I noticed reviewing the smbios code cleanup diff.kmos1-2/+2
2019-08-04Cleanup the bios(4)/smbios(4) code a bit. Fix some KNF issues, reducekettenis2-142/+156
2019-07-26emove duplicate definitions of LAPIC_ID_MASK and LAPIC_ID_SHIFT.kevlo1-3/+1
2019-06-28Write back and invalidate caches before updating CPU microcode,bluhm1-2/+2
2019-06-14Add TSC_ADJUST CPUID flag.kettenis1-1/+2
2019-04-10change marks[] array to uint64_t, so the code can track full 64-bitderaadt1-2/+2
2019-03-23Use the debugger mutex for `ddb_mp_mutex'. This should prevent a racevisa1-2/+2
2019-01-22flense more trailing whitespacephessler1-4/+4
2019-01-22remove trailing whitespace in the Laptop Package part of the license text.phessler1-4/+4
2019-01-18delete vmm(4) in i386pd7-1332/+8
2018-12-05Include srp.h where struct cpu_info uses srp to avoid erroring out whenjsg1-1/+2
2018-10-02Unify the MD byteswapping code as much as possible across architectures.naddy1-22/+23
2018-09-11Add defines for amd microcode msrs which appear to be present since k8jsg1-1/+3
2018-08-29First pass in bringing i386 in sync with amd64. This does not yet work, but ispd1-1/+43
2018-08-25Define __HAVE_ACPI.kettenis1-1/+3
2018-08-23port the amd64 code for loading intel microcode on boot to i386jsg3-3/+13
2018-08-21print rdtscp and xsave_ext cpuid bits on i386 as welljsg1-1/+22
2018-08-21print sefflags_edx cpuid bits on i386 as welljsg1-1/+2
2018-08-20Remove unused spllock().visa1-2/+1
2018-08-15add cpuid and msr bits fromjsg1-6/+21
2018-08-08Recognise 'Speculative Store Bypass Disable' support cpuid bit.jsg1-1/+2
2018-07-30Use the MI interrupt enable/distable API instead of the MD one on i386 andkettenis1-17/+3
2018-07-24Do the same for i386 as amd64:brynet1-1/+2
2018-07-12unbreak i386 build, thanks to pd@ for noticing. Same diff as I committedmlarkin1-6/+16
2018-07-09Delete the VM86 kernel option and i386_vm86(3) API: it's requiredguenther4-189/+3
2018-06-30Add intr_enable() function, intended for MI use to amd64 and i386 and usekettenis1-1/+7
2018-06-22Finish the last missing piece for the i386 meltdown fix:bluhm4-26/+32
2018-06-21Save and restore retguard area during hibernate unpack. This copies themlarkin1-2/+2
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