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* Bump MAXTSIZ to 256MB on i386.kurt2021-03-161-2/+2
* spellingjsg2021-03-117-14/+14
* Geode CPU does not support SSE, so MXCSR does not exists there. Asbluhm2020-12-131-3/+2
* Introduce constants to access the setjmp(3) jmp_buf fields frombluhm2020-12-061-2/+13
* the legacy need_resched macro to access per-cpu value is no longer neededderaadt2020-09-241-3/+1
* When operating in NX mode, GUCODE_SEL can cover the entire userlandderaadt2020-09-241-1/+2
* Make sure we fetch the CS limit of the CPU the trap happened on. It iskettenis2020-09-242-3/+5
* shuffle "extern int cpu_pae" into cpu.h, as the number of users will soonderaadt2020-09-231-1/+2
* add an ipi for wbinvd and a linux style wbinvd_on_all_cpus() functionjsg2020-09-132-4/+16
* add SRBDS cpuid bitsjsg2020-09-131-1/+6
* Add support for timeconting in userland.pirofti2020-07-061-0/+23
* Remove obsolete <machine/stdarg.h> header. Nowadays the varargvisa2020-06-301-54/+0
* introduce "cpu_rnd_messybits" for use instead of nanotime in dev/rnd.c.dlg2020-05-311-1/+3
* Retire <machine/varargs.h>.visa2020-05-271-58/+0
* Kill unused cdev_pc_init().mpi2020-05-251-10/+1
* Kill biospoll/pctrpoll defines and use `seltrue' directly in cdev_*_init().mpi2020-05-131-3/+1
* Use the same inittodr()/resettodr() implementation as onkettenis2020-04-291-2/+2
* controler -> controllerjsg2020-02-201-3/+3
* Disable TSX when MSR_ARCH_CAPABILITIES sets TSX_CTRL.jsg2019-12-202-2/+10
* Convert boolean_t/TRUE/FALSE to int/1/0 for coherency with the rest ofmpi2019-12-191-18/+18
* Remove kernel VM86 support.mpi2019-12-081-43/+0
* Convert db_addr_t -> vaddr_t but leave the typedef for now.mpi2019-11-071-2/+2
* Fix a typo I noticed reviewing the smbios code cleanup diff.kmos2019-08-041-2/+2
* Cleanup the bios(4)/smbios(4) code a bit. Fix some KNF issues, reducekettenis2019-08-042-142/+156
* emove duplicate definitions of LAPIC_ID_MASK and LAPIC_ID_SHIFT.kevlo2019-07-261-3/+1
* Write back and invalidate caches before updating CPU microcode,bluhm2019-06-281-2/+2
* Add TSC_ADJUST CPUID flag.kettenis2019-06-141-1/+2
* change marks[] array to uint64_t, so the code can track full 64-bitderaadt2019-04-101-2/+2
* Use the debugger mutex for `ddb_mp_mutex'. This should prevent a racevisa2019-03-231-2/+2
* flense more trailing whitespacephessler2019-01-221-4/+4
* remove trailing whitespace in the Laptop Package part of the license text.phessler2019-01-221-4/+4
* delete vmm(4) in i386pd2019-01-187-1332/+8
* Include srp.h where struct cpu_info uses srp to avoid erroring out whenjsg2018-12-051-1/+2
* Unify the MD byteswapping code as much as possible across architectures.naddy2018-10-021-24/+25
* Add defines for amd microcode msrs which appear to be present since k8jsg2018-09-111-1/+3
* First pass in bringing i386 in sync with amd64. This does not yet work, but ispd2018-08-291-1/+43
* Define __HAVE_ACPI.kettenis2018-08-251-1/+3
* port the amd64 code for loading intel microcode on boot to i386jsg2018-08-233-3/+13
* print rdtscp and xsave_ext cpuid bits on i386 as welljsg2018-08-211-1/+22
* print sefflags_edx cpuid bits on i386 as welljsg2018-08-211-1/+2
* Remove unused spllock().visa2018-08-201-2/+1
* add cpuid and msr bits fromjsg2018-08-151-6/+21
* Recognise 'Speculative Store Bypass Disable' support cpuid bit.jsg2018-08-081-1/+2
* Use the MI interrupt enable/distable API instead of the MD one on i386 andkettenis2018-07-301-17/+3
* Do the same for i386 as amd64:brynet2018-07-241-1/+2
* unbreak i386 build, thanks to pd@ for noticing. Same diff as I committedmlarkin2018-07-121-6/+16
* Delete the VM86 kernel option and i386_vm86(3) API: it's requiredguenther2018-07-094-189/+3
* Add intr_enable() function, intended for MI use to amd64 and i386 and usekettenis2018-06-301-1/+7
* Finish the last missing piece for the i386 meltdown fix:bluhm2018-06-224-26/+32
* Save and restore retguard area during hibernate unpack. This copies themlarkin2018-06-211-2/+2
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