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* Userland timecounter implementation for octeonvisa2020-07-181-2/+2
| | | | OK naddy@; no objections from kettenis@
* Add support for timeconting in userland.pirofti2020-07-061-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | This diff exposes parts of clock_gettime(2) and gettimeofday(2) to userland via libc eliberating processes from the need for a context switch everytime they want to count the passage of time. If a timecounter clock can be exposed to userland than it needs to set its tc_user member to a non-zero value. Tested with one or multiple counters per architecture. The timing data is shared through a pointer found in the new ELF auxiliary vector AUX_openbsd_timekeep containing timehands information that is frequently updated by the kernel. Timing differences between the last kernel update and the current time are adjusted in userland by the tc_get_timecount() function inside the MD usertc.c file. This permits a much more responsive environment, quite visible in browsers, office programs and gaming (apparently one is are able to fly in Minecraft now). Tested by robert@, sthen@, naddy@, kmos@, phessler@, and many others! OK from at least kettenis@, cheloha@, naddy@, sthen@
* Remove obsolete <machine/stdarg.h> header. Nowadays the varargvisa2020-06-301-3/+0
| | | | | | | | functionality is provided by <sys/stdarg.h> using compiler builtins. Tested in a ports bulk build on amd64 by naddy@ OK naddy@ mpi@
* Retire <machine/varargs.h>.visa2020-05-271-3/+0
| | | | | | Nothing uses the header anymore. OK deraadt@ mpi@
* Fix some of the more esoteric bus_space functions. Thekettenis2020-04-141-7/+8
| | | | | | | | | | bus_space_read_region_n, bus_space_write_region_n and bus_space_set_region_n functions were all broken. Same fix as arm64; Thanks to patrick@ for noting that mips64 had the same code. ok visa@
* Implement splassert() on mips64.visa2019-09-051-1/+17
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* Adjust interrupt priority levels on mips64 so that prioritiesvisa2019-09-051-24/+21
| | | | | | of soft interrupts are lower than priorities of hard interrupts. This allows the delivery of hard interrupts while soft interrupts are masked.
* flense more trailing whitespacephessler2019-01-221-5/+5
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* remove trailing whitespace in the Laptop Package part of the license text.phessler2019-01-221-4/+4
| | | | no words or punctation were modified.
* Remove unused spllock().visa2018-08-201-2/+1
| | | | OK deraadt@ mpi@
* Save and restore retguard area during hibernate unpack. This copies themlarkin2018-06-211-2/+2
| | | | | | | original retguard data to the piglet and bcopys it back in place immediately before resuming via the ACPI Sx trampoline. ok deraadt, guenther, tested by many.
* Include <sys/mutex.h> instead of <machine/mutex.h>mpi2018-01-221-2/+2
| | | | required by upcoming MI mutex change.
* Add a dummy (for now) <machine/reloc.h> for mips64 to fix build.visa2017-08-121-0/+5
| | | | OK guenther@
* Define MAXCPUS per mips64 port.visa2017-07-301-1/+2
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* Define register_splx_handler() in one place.visa2017-06-111-13/+2
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* Enable radeondrm(4) on loongson to get accelerated graphicsvisa2017-05-213-4/+6
| | | | | | with the RS780E chipset. OK kettenis@, jsg@
* Make IPL_MPSAFE effective on loongson.visa2017-05-171-2/+2
| | | | Testing help from fcambus@
* Add a PCI attach hook mechanism for htb(4), similar to the onevisa2017-05-101-1/+3
| | | | | | in bonito(4). Use the hook for setting up the PIC. Discussed with miod@ long ago
* add a BUS_DMA_64BIT flag to bus_dma on all our archs.dlg2017-05-081-1/+2
| | | | | | | | | this is so drivers can advertise that they can handle 64 dma addresses to the platform. it may choose to handle dmamaps differently based on this flag. tweaks and ok tom@ ok kettenis@
* Add SMP config and IPI control logic for Loongson 3A.visa2017-02-192-3/+9
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* Extend struct platform with MP control functions, and add bootstrap codevisa2017-01-193-3/+31
| | | | | | for secondary CPUs. Discussed with miod@
* Add mplock.h for loongson.visa2017-01-191-0/+3
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* Determine the available CPUs.visa2016-12-111-1/+5
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* Fix CPU info struct.visa2016-11-221-2/+3
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* Use the ErrorEPC register for curcpu().visa2016-11-181-1/+7
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* Add drivers for PCI host bridge and built-in UARTs on Loongson 3A,visa2016-11-171-2/+3
| | | | | | and put the pieces together by platform glue. Feedback from miod@
* Add interrupt handling routines for Loongson 3A.visa2016-11-062-1/+26
| | | | Feedback from miod@
* Move the definition of REGVAL into a common header to make it usablevisa2016-11-051-1/+7
| | | | | | outside bonito(4). ok miod@
* Initial support for MSI-X. Only supported on amd64 for now. I have diffs tokettenis2016-05-041-1/+2
| | | | | | | | | | actually use this in em(4) and xhci(4), but I'm not committing those yet because we almost certainly need to save and restore the MSI-X registers during suspend/resume. However, this allows mpi@ to play with multiple-vector support in networking hardware. Requested by mpi@ ok mlarkin@, mikeb@
* Rename mips64's trap_frame into trapframe.mpi2016-03-061-3/+3
| | | | | | For coherency with other archs and in order to use it in MI code. ok visa@, tobiasu@
* Some implementations of HitSyncDCache() call pmap_extract() for va->pavisa2016-01-051-1/+5
| | | | | | | | | | | | | | | | | | conversion. Because pmap_extract() acquires the PTE mutex, a "locking against myself" panic is triggered if the cache routine gets called in a context where the mutex is already held. In the pmap, all calls to HitSyncDCache() are for a whole page. Add a new cache routine, HitSyncDCachePage(), which gets both the va and the pa of a page. This removes the need of the va->pa conversion. The new routine has the same signature as SyncDCachePage(), allowing reuse of the same routine for cache implementations that do not need differences between "Hit" and non-"Hit" routines. With the diff, POWER Indigo2 R8000 boots multiuser again. Tested on sgi GENERIC-IP27.MP and octeon GENERIC.MP, too. Diff from miod@, ok kettenis@
* Use #ifndef _MACHINE_DISKLABEL_H_ everywhere. Replace _ARM_DISKLABEL_H_krw2015-09-301-1/+6
| | | | | | and _SH_DISKLABEL_H_ with _MACHINE_DISKLABEL_H_. Add the guard to loongson and octeon. The #defines are not used anywhere else in the tree so no functional change.
* Use consistant whitespace/comments for #define'ing LABELSECTOR,krw2015-09-301-4/+4
| | | | | LABELOFFSET and MAXPARTITIONS. Easier on the eye when scanning through all these files. No functional change.
* intr_barrier(9) for loongson, octeon and sgi.kettenis2015-09-131-1/+3
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* Some bits for Loongson 3A support.miod2015-08-151-1/+22
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* Remove {LOAD,COUNT}_TEXTA from libsa loadfile, it only made sense for a.outmiod2015-07-171-3/+3
| | | | kernels and we no longer have any.
* unify the mutex implementations on all the mips64 platforms.dlg2015-07-082-61/+5
| | | | | | | | this basically copies the sgi implementation to mips64 and removes it from the rest. this way they get an optimised UP mutex implementation and correct asserts on all platforms. ok miod@ jmatthew@
* APM_USER_HIBERNATE_REQ here too.miod2015-02-071-1/+2
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* Remove some unused code that we added at the 2013 Toronto hackathon butmlarkin2014-05-311-2/+1
| | | | don't need anymore.
* Provide bus_space_mmap()miod2014-05-241-1/+6
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* Due the virtually indexed nature of the L1 instruction cache on most mipsmiod2014-03-311-1/+5
| | | | | | | | | | | | | | | | | | | | processors, every time a new text page is mapped in a pmap, the L1 I$ is flushed for the va spanned by this page. Since we map pages of our binaries upon demand, as they get faulted in, but uvm_fault() tries to map the few neighbour pages, this can end up in a bunch of pmap_enter() calls in a row, for executable mappings. If the L1 I$ is small enough, this can cause the whole L1 I$ cache to be flushed several times. Change pmap_enter() to postpone these flushes by only registering the pending flushes, and have pmap_update() perform them. The cpu-specific cache code can then optimize this to avoid unnecessary operations. Tested on R4000SC, R4600SC, R5000SC, RM7000, R10000 with 4KB and 16KB page sizes (coherent and non-coherent designs), and Loongson 2F by mikeb@ and me. Should not affect anything on Octeon since there is no way to flush a subset of I$ anyway.
* Update the loongson codebase to recognize the so-called `EFI-like' interfacemiod2014-03-292-4/+160
| | | | | supposedly provided by newer PMON firmware (on Loongson 2Gq and Loongson 3A systems).
* It's been a quarter century: we can assume volatile is present with that name.guenther2014-03-291-2/+2
| | | | ok dlg@ mpi@ deraadt@
* Remove dependency from wscons_machdep upon bonito. Instead of hardcoding bonitomiod2014-03-272-4/+7
| | | | | | | | as the northbridge, have the per-platform early setup code register functions providing access to the PCI configuration space, for the wscons code to walk the PCI space in search of a graphics board. No functional change yet.
* Increase VM_PHYSSEG_MAX, necessary for systems with non-contiguous memorymiod2014-03-271-2/+2
| | | | (such as 2E and 3A systems).
* Support BUS_DMA_NOCACHE in bus_dma(9). Memory allocations done withmiod2014-03-101-14/+15
| | | | | | BUS_DMA_NOCACHE (or BUS_DMA_COHERENT if the platform does not have coherent caches) will use PMAP_NOCACHE when invoking pmap_enter(), to avoid creating cached mappings, and then evicting them from the cache.
* Add a stub for the new MD hook needed to handle ACPI Power Resources.mpi2013-11-051-1/+2
| | | | ok kettenis@
* Start working on hibernate support for Loongsonpirofti2013-06-022-0/+73
| | | | | | | This is work in progress. Nothing to test or play with for now. Commiting it now so that I can work on it in-tree. Okay miod@
* add missing license (PD) blockjasper2013-06-012-4/+4
| | | | ok guenther@
* Add a dummy IPL_MPSAFE definition.kettenis2013-05-171-1/+4
| | | | ok miod@, mikeb@
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