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path: root/sys/arch/sgi/xbow/xbridge.c (follow)
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* Disambiguate expressions.visa2021-03-211-3/+3
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* spellingjsg2021-03-111-7/+7
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* The device_to_pa routine really isn't needed. We always have physicalvisa2017-05-111-11/+6
| | | | | | | addresses. While there, pave the way for BUS_DMA_64BIT (not working yet). Diff from miod@; OK dlg@
* Let MP-safe interrupt handlers run without the kernel lock on sgi.visa2017-02-111-4/+26
| | | | OK miod@
* Let the IP27 kernel build with DEBUG.visa2015-12-031-9/+9
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* free(x, 0) cleanup:semarie2015-09-271-9/+7
| | | | | | | - set size argument of free() - remove pointless if expression around free() call ok guenther@
* Also print the error registers in the ddb callback.miod2015-09-121-1/+7
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* sizes for free(); ok semariederaadt2015-09-081-3/+3
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* Attempt to explain how this device works. Based upon a private mail I wrotemiod2015-06-241-1/+231
| | | | 6 years ago when asked about this.
* Clear the PIC `write request' memory at initialization time. There ismiod2015-06-161-1/+18
| | | | apparently a risk of spurious parity errors if we don't.
* Add an helper routine if defined(DDB), which might help figuring out whymiod2015-03-231-1/+32
| | | | PIC sometimes loses isp^Wqlw interrupts.
* Move the PIC revision 1 interrupt workaround from xbridge_pci_intr_handler()miod2014-12-041-14/+31
| | | | | | | | to a dedicated wrapper function, and register either xbridge_pci_intr_handler() or the wrapper as the interrupt handler, depending upon which chip we run on. Saves the cost of the workaround on non-affected chips, which are a large majority.
* implement atomic operations using ll/sc, and convert rw_cas and callers of thejmatthew2014-09-301-2/+2
| | | | | | | pre-existing atomics to match. tested on sgi (octane) and octeon (erl) ok miod@ dlg@
* More PIC programming magic, as well as a specific workaround for lostmiod2014-08-191-5/+27
| | | | | | | interrupts in PIC rev 1; from IRIX via Linux 2.5.69. This doesn't fix the lost SCSI interrupts jasper@ eventually experiences on Origin 350 systems, but this can't hurt anyway.
* add a size argument to free. will be used soon, but for now default to 0.tedu2014-07-121-8/+8
| | | | after discussions with beck deraadt kettenis.
* Format string fixes and removal of -Wno-format for sgi. Based upon anmiod2014-05-191-3/+3
| | | | initial diff from jasper@
* Moar <uvm/uvm.h> -> <uvm/uvm_extern.h> love.mpi2014-04-031-2/+2
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* add missing arguments to debug printfsjsg2014-01-221-3/+3
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* Proide a mips_sync() macro to wrap asm("sync"), and replace gazillions ofmiod2012-09-291-2/+2
| | | | such statements with it.
* Make sure the generic bus_dmamem_alloc() routine restricts its allocation tomiod2012-05-201-182/+7
| | | | | | the dma_constraint range. This allows the xbridge(4) bus_dma_tag_t to use the generic routines instead of rolling its own, now that the ATE code has been removed.
* Extend pci_probe_device_hook() on sgi xbridge(4) to return either the straightmiod2011-10-101-59/+113
| | | | | | | | | | | accessors or the byte-swapped accessors, depending upon the byteswap setting of the device we are trying to attach. This allows for the removal of byteswap knowledge from ioc(4) and iof(4) drivers. While there, build pci_chipset_t md structs by bcopy'ing a template and filling the few runtime fields, instead of assigning every field of them.
* Introduce pci_probe_device_hook(pci_chipset_tag_t, struct pci_attach_args *).miod2011-10-101-1/+13
| | | | | | | | | | | | | | | | | | This mandatory function will get invoked in pci_probe_device(), and allows a pci host driver to alter the pci_attach_args passed to a device when attaching. This function will also, if returning non-zero, cause the device to be skipped completely during all the phases of the PCI device discovery (i.e. ressource enumeration, ressource assignment, and actual attachment). This particular feature is experimental and might be reverted in the future (or the scope narrowed to device attachment only). A dummy #define pci_probe_device_hook() 0 is added to all platforms except sgi, where real functions (currently only returning 0) are added; real meat will be added shortly. Discussed at s2k11, no objection from the usual suspects.
* On IP27 systems, fill the array of node hub widget numbers early, so that allmiod2011-04-171-7/+17
| | | | | | hubs are known during autoconf. Then, pick the most populated 2GB window as our DMA memory window. xbridge(4) can thus program the correct settings regardless of the order in which the xbow(4) attach.
* Rename a few xbow global variable names to make them less ambiguous.miod2011-04-051-13/+26
| | | | | | | | | Remember the hub widget number of each node, instead of only the master node. Use this in xbridge to compute the proper direct DMA map configuration register value (it needs to embed the hub widget number matching the physical address range). This should allow us to pick memory from a different node than the one we booted from, as the DMA window, if wanted.
* Get rid of the ATE code, and do not assume the direct DMA window is set upmiod2011-04-051-425/+28
| | | | | | at physical address zero onwards, but instead assume it is controlled by the dma_constraints range. This will eventually allow a different window to be selected.
* Disable write gathering on devio settings we inherit from ARCS.miod2011-03-131-17/+25
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* Introduce a new pci routine, pci_conf_size(), which returns the size of amiod2010-12-041-1/+27
| | | | | | | given pcitag_t configuration address space. Currently, all pci controllers will return the usual 0x100 bytes of PCI configuration space, but this will eventually change on PCIe-capable controlers. ok kettenis@
* Missed one rbus_new_body() call in previous change.miod2010-11-271-5/+3
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* remove unused offset argument to rbus functionsjsg2010-09-221-4/+4
| | | | ok krw@ kettenis@
* Get rid of evcount's support for arranging counters in a treematthew2010-09-201-2/+2
| | | | | | | hierarchy. Everything attached to a single root node anyway, so at best we had a bush. "i think it is good" deraadt@
* Implement bus_space_barrier() on sgi; on xbridge, this will also flushmiod2010-08-231-1/+50
| | | | the pci write buffers.
* Rework the logic of xbridge pci_conf_{read,write} to avoid doing the disablemiod2010-08-231-49/+54
| | | | | bridge interrupts dance when trying to access an uninplemented ioc3 register. Makes PIC handling simpler as a bonus.
* Program a larger PCI retry hold interval if there is a Lucent USB controllermiod2010-05-091-1/+20
| | | | | on the bus, to workaround timeout problems, according to IRIX knowledge which made its way to Linux.
* more cleanup to cope with the change that tries to make proc.h not actderaadt2010-04-211-1/+2
| | | | | like it is everything.h ok tedu
* Obtain struct sgi_device_location for the console input and output devices,miod2010-04-061-8/+20
| | | | | and compare against them when attaching potential console drivers, to figure out whether they indeed are acting are console devices or not.
* Remove parent/slave mode of rbus as nothing uses it.jsg2010-04-021-2/+2
| | | | ok kettenis, sgi usage of rbus_new_body() pointed out by miod
* Correctly account devio usage, instead of relying upon unused devio registersmiod2010-03-281-66/+108
| | | | | | | | | being set to zero; this allows a full PIC bus to correctly configure I/O resources. While there, when initializing a ppb, setup I/O resources before memory resources; without this a ppb connected to a PIC could not get I/O resources if devices behind it would use both I/O and memory resources.
* Add an MD interface for PCI drivers to be able to retrieve the node and widgetmiod2010-03-071-1/+21
| | | | | number the PCI bus they are on is connected to. Will be used shortly to help the console device selection logic.
* Register an interrupt handler for PCI error conditions (as well as xtalkmiod2009-12-261-19/+170
| | | | errors at the widget level). Extremely crude for now.
* Pass both the virtual address and the physical address of the memory rangemiod2009-12-251-7/+9
| | | | | | | | | | when invoking the cache functions. The physical address is needed when operating on physically-indexed caches, such as the L2 cache on Loongson processors. Preprocessor abuse makes sure that the physical address computation gets compiled out when running on a kernel compiled for virtually-indexed caches only, such as the sgi kernel.
* Allow xbow_intr_establish() callers to provide optional storage for themiod2009-11-251-2/+2
| | | | struct intrhand, instead of having it malloc()'ed.
* It turns out that the 2GB contiguous DMA direct map window also needsmiod2009-11-191-41/+15
| | | | | | | | | | | | | | | to be aligned on a 2GB boundary. Therefore the `add 512MB' bit used on Octane does not give us a 0.5GB-2.5GB usable DMA range, but a 0.5GB-2GB range; trying to use address in the 2GB-2.5GB range would cause PCI DMA errors at the xbridge level. There is no real benefit in using it, since this required us to keep subtracting or adding 0.5GB when converting DMA address to physical memory address or the other way around. So stop using it; this makes a few parts of the code simpler (and until bounce buffers are implemented, Octane systems will not use more than 1.5GB of memory).
* Move widget register information apart from xbow software interface, andmiod2009-11-181-1/+2
| | | | update #include needs. No functional change.
* It turns out PCI IOC3 card which embed both the Ethernet controller and themiod2009-11-111-19/+42
| | | | | | | | | | | | | | | superio chip interrupt on two different pins (yet do not advertize themselves as a multi-function device, of course). So, on one hand, this makes the ioc attachment code simpler, because it simply needs to map interrupt pins A and B, and another hand, this moves all the interrupt knowledge to the PCI bridge driver, since routing of pin B differs whether the device is the onboard IOC3 chip (and able to use any of the 8 bridge interrupt sources...) or on a PCI board (with pin mapping sane, since controlled by the bridge). This makes superio interrupts on CADduo boards work. Tested to cause no regressions on Origin 200, Octane and Fuel.
* Replace option TGT_ORIGIN200 and TGT_ORIGIN2000 with a single option,miod2009-11-071-7/+7
| | | | | | | | | | TGT_ORIGIN, which enables support for all IP27 and IP35 systems. The original two options have always been used together, and go back to when pefo thought supporting multiple nodes would be significant work. Since an Origin 200 can be a dual-node system, making a distinction between single node and multiple node systems is a moot point anyway. Be sure to rerun config(8) before rebuilding a kernel.
* Change sgi system identification from a single system type list, to a smallermiod2009-11-071-3/+3
| | | | | | system type list (which really is the system family) and a subsystem type. No functional change yet.
* Make pci_intr_string() on xbridge return both the xbridge irq and the crossbowmiod2009-10-261-28/+42
| | | | | | irq we route it to; this makes clear that devices connected to different xbridges but using the same xbridge irq are actually not shared at all; and this also helps figure out which device cause spurious interrupts.
* Add support for the Octane power button to power(4). Took me a while tomiod2009-10-261-4/+18
| | | | | figure out how the interrupt was routed from xbridge to xheart... (it bypasses the regular `have xbridge send a xio interrupt packet' mechanism)
* Add new xbow routines to explicitely trigger or clear an interrupt source,miod2009-10-261-24/+3
| | | | | instead of embedding that knowledge in xbridge(4); will be used elsewhere shortly.
* Completely overhaul interrupt handling on sgi. Cpu state now only stores amiod2009-10-221-2/+9
| | | | | | | | | | | | | | | | logical IPL level, and per-platform (IP27/IP30/IP32) code will from the necessary hardware mask registers. This allows the use of more than one interrupt mask register. Also, the generic (platform independent) interrupt code shrinks a lot, and the actual interrupt handler chains and masking information is now per-platform private data. Interrupt dispatching is generated from a template; more routines will be added to the template to reduce platform-specific changes and share as much code as possible. Tested on IP27, IP30, IP32 and IP35.
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