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path: root/sys/arch/sgi/xbow/xbridge.c (follow)
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* Disambiguate expressions.visa2021-03-211-3/+3
* spellingjsg2021-03-111-7/+7
* The device_to_pa routine really isn't needed. We always have physicalvisa2017-05-111-11/+6
* Let MP-safe interrupt handlers run without the kernel lock on sgi.visa2017-02-111-4/+26
* Let the IP27 kernel build with DEBUG.visa2015-12-031-9/+9
* free(x, 0) cleanup:semarie2015-09-271-9/+7
* Also print the error registers in the ddb callback.miod2015-09-121-1/+7
* sizes for free(); ok semariederaadt2015-09-081-3/+3
* Attempt to explain how this device works. Based upon a private mail I wrotemiod2015-06-241-1/+231
* Clear the PIC `write request' memory at initialization time. There ismiod2015-06-161-1/+18
* Add an helper routine if defined(DDB), which might help figuring out whymiod2015-03-231-1/+32
* Move the PIC revision 1 interrupt workaround from xbridge_pci_intr_handler()miod2014-12-041-14/+31
* implement atomic operations using ll/sc, and convert rw_cas and callers of thejmatthew2014-09-301-2/+2
* More PIC programming magic, as well as a specific workaround for lostmiod2014-08-191-5/+27
* add a size argument to free. will be used soon, but for now default to 0.tedu2014-07-121-8/+8
* Format string fixes and removal of -Wno-format for sgi. Based upon anmiod2014-05-191-3/+3
* Moar <uvm/uvm.h> -> <uvm/uvm_extern.h> love.mpi2014-04-031-2/+2
* add missing arguments to debug printfsjsg2014-01-221-3/+3
* Proide a mips_sync() macro to wrap asm("sync"), and replace gazillions ofmiod2012-09-291-2/+2
* Make sure the generic bus_dmamem_alloc() routine restricts its allocation tomiod2012-05-201-182/+7
* Extend pci_probe_device_hook() on sgi xbridge(4) to return either the straightmiod2011-10-101-59/+113
* Introduce pci_probe_device_hook(pci_chipset_tag_t, struct pci_attach_args *).miod2011-10-101-1/+13
* On IP27 systems, fill the array of node hub widget numbers early, so that allmiod2011-04-171-7/+17
* Rename a few xbow global variable names to make them less ambiguous.miod2011-04-051-13/+26
* Get rid of the ATE code, and do not assume the direct DMA window is set upmiod2011-04-051-425/+28
* Disable write gathering on devio settings we inherit from ARCS.miod2011-03-131-17/+25
* Introduce a new pci routine, pci_conf_size(), which returns the size of amiod2010-12-041-1/+27
* Missed one rbus_new_body() call in previous change.miod2010-11-271-5/+3
* remove unused offset argument to rbus functionsjsg2010-09-221-4/+4
* Get rid of evcount's support for arranging counters in a treematthew2010-09-201-2/+2
* Implement bus_space_barrier() on sgi; on xbridge, this will also flushmiod2010-08-231-1/+50
* Rework the logic of xbridge pci_conf_{read,write} to avoid doing the disablemiod2010-08-231-49/+54
* Program a larger PCI retry hold interval if there is a Lucent USB controllermiod2010-05-091-1/+20
* more cleanup to cope with the change that tries to make proc.h not actderaadt2010-04-211-1/+2
* Obtain struct sgi_device_location for the console input and output devices,miod2010-04-061-8/+20
* Remove parent/slave mode of rbus as nothing uses it.jsg2010-04-021-2/+2
* Correctly account devio usage, instead of relying upon unused devio registersmiod2010-03-281-66/+108
* Add an MD interface for PCI drivers to be able to retrieve the node and widgetmiod2010-03-071-1/+21
* Register an interrupt handler for PCI error conditions (as well as xtalkmiod2009-12-261-19/+170
* Pass both the virtual address and the physical address of the memory rangemiod2009-12-251-7/+9
* Allow xbow_intr_establish() callers to provide optional storage for themiod2009-11-251-2/+2
* It turns out that the 2GB contiguous DMA direct map window also needsmiod2009-11-191-41/+15
* Move widget register information apart from xbow software interface, andmiod2009-11-181-1/+2
* It turns out PCI IOC3 card which embed both the Ethernet controller and themiod2009-11-111-19/+42
* Replace option TGT_ORIGIN200 and TGT_ORIGIN2000 with a single option,miod2009-11-071-7/+7
* Change sgi system identification from a single system type list, to a smallermiod2009-11-071-3/+3
* Make pci_intr_string() on xbridge return both the xbridge irq and the crossbowmiod2009-10-261-28/+42
* Add support for the Octane power button to power(4). Took me a while tomiod2009-10-261-4/+18
* Add new xbow routines to explicitely trigger or clear an interrupt source,miod2009-10-261-24/+3
* Completely overhaul interrupt handling on sgi. Cpu state now only stores amiod2009-10-221-2/+9