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* Add a guard page between I/O virtual address space allocations. The ideapatrick2021-04-031-3/+4
* Exclude the first page from I/O virtual address space, which is the NULLpatrick2021-04-031-3/+4
* Fix Dale's email addresstb2021-04-024-8/+8
* Turns out the PCIe DARTs support a full 32-bit device virtual address space.kettenis2021-03-291-4/+9
* Fix IA32_EPT_VPID_CAP_XO_TRANSLATIONS specificationdv2021-03-291-2/+2
* Make sure that all CPUs end up with the same bits set in SCTLR_EL1.kettenis2021-03-272-27/+28
* Add ARMv8.5 instruction set related CPU features.kettenis2021-03-272-4/+184
* Return EOPNOTSUPP for unsupported ioctlskn2021-03-261-16/+6
* Fix "mach dtb" return code to avoid bogus bootkn2021-03-261-6/+8
* Fix errno, merge ioctl caseskn2021-03-261-13/+5
* remove uneeded includes in md armv7 filesjsg2021-03-2569-307/+71
* The logic in mmrw() to check whether an address is within directbluhm2021-03-241-4/+4
* Pack the SPCR struct definition since the struct isn't naturally alignedpatrick2021-03-231-2/+2
* Now that MSI pages are properly mapped, all that debug code in smmu(4)patrick2021-03-221-34/+2
* Load MSI pages through bus_dma(9). Our interrupt controllers for MSIspatrick2021-03-224-18/+100
* Disambiguate expressions.visa2021-03-211-3/+3
* another unfortunate action to cope with relentless kernel growthderaadt2021-03-191-2/+2
* Add missing memory clobbers to "data" barriers.kettenis2021-03-173-11/+11
* Always use an allocated buffer for {Read,Write}Blocks() to makeyasuoka2021-03-172-80/+34
* Node without a "status" property should be considered enabled as well.kettenis2021-03-161-3/+3
* Make sure that switching the console from serial to framebuffer workskettenis2021-03-162-22/+25
* acpi_intr_disestablish() should free its own cookie.patrick2021-03-161-1/+2
* Bump MAXTSIZ to 256MB on i386.kurt2021-03-161-2/+2
* Fix some correctness issues in the lowelevel kernel bringup code.kettenis2021-03-163-5/+20
* Add code to acpiiort(4) to look up named components in the IORT andpatrick2021-03-153-4/+80
* Change API of acpiiort(4). It was written as a hook before, taking thepatrick2021-03-157-33/+23
* Add acpi_iommu_device_map(), which replaces the DMA tag with one thatpatrick2021-03-153-3/+21
* Don't put an extern variable (ppc_kvm_stolen) into vmparam.h, other instancesderaadt2021-03-152-6/+3
* We can use memory marked as EfiBootServicesCode or EfiBootServicesDatakettenis2021-03-131-3/+6
* spellingjsg2021-03-11140-331/+331
* Add SMP support.kettenis2021-03-111-14/+99
* grow media a littlederaadt2021-03-111-2/+2
* Let MAIR comment catch up with reality.kettenis2021-03-101-2/+5
* pmap_avail_setup() is the only place physmem is calculated, delete a bunchderaadt2021-03-101-9/+2
* Node without a "status" property should be considered enabled as well.kettenis2021-03-091-3/+3
* Recognize Apple Firestorm cores.kettenis2021-03-091-1/+3
* Add initial bits for Check Point UTM-1 EDGE N.visa2021-03-093-3/+15
* ofw_read_mem_regions() can skip calculation of physmem. pmap.cderaadt2021-03-091-5/+1
* Enable ixl(4).patrick2021-03-082-2/+4
* Revise the ASID allocation sheme to avoid a hang when running out of freekettenis2021-03-082-31/+120
* Explicitly align kernel text.mortimer2021-03-072-5/+6
* Since with the current design there's one device per domain, and onepatrick2021-03-061-17/+11
* One major issue talked about in research papers is reducing the overheadpatrick2021-03-061-61/+103
* ansijsg2021-03-062-6/+4
* Improve readability of softc accesses.patrick2021-03-051-13/+20
* Introduce an IOVA allocator instead of mapping pages 1:1. Mapping pages 1:1patrick2021-03-052-106/+129
* Extend the commented code that shows which additional mappings are needed,patrick2021-03-051-6/+24
* Turns out the cores on Apple's M1 SoC only support 8-bit ASIDs.kettenis2021-03-041-52/+57
* Print feature that indicates a CPU core supports 16-bit ASIDs.kettenis2021-03-041-1/+13
* Tweak whitespace and adjust prototypes.visa2021-03-041-23/+21