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path: root/sys/dev/fdt/dwpcie.c (follow)
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* Load MSI pages through bus_dma(9). Our interrupt controllers for MSIspatrick2021-03-221-4/+53
* Transactions on the AXI bus contain a Stream ID. SMMUs filterpatrick2021-03-011-1/+15
* Issue call to IOMMU OFW API to collect an IOMMU-sprinkled DMA tag.patrick2021-02-281-1/+7
* Add some infrastructure in the PCI chipset tag for pci_probe_device_hook()patrick2021-02-251-1/+9
* Add support for the PCIe controller found on Amlogic G12A/G12B/SM1 SoCs.kettenis2020-12-281-11/+119
* Defer hardware initialization in order to give things like PCIe PHYskettenis2020-12-221-15/+31
* Implement pci_intr_establish_cpu() on arm64 and armv7. The function pointerpatrick2020-07-141-10/+7
* Increase chances of getting a successful PCIe link on the i.MX8MM.patrick2020-05-231-3/+2
* PCIe register accesses seem to "hang" on the i.MX8MM if its PHY doesn'tpatrick2020-04-271-14/+38
* Free the "ranges" array in the error handling paths.patrick2020-04-271-1/+7
* Add i.MX8MM support to dwpcie(4). This re-uses the existing codepatrick2020-04-261-18/+98
* Enable pcie_aux in addition to the other PCIe clocks on i.MX8M.patrick2020-04-231-1/+2
* Since apparently the bikeshedding over i.MX8M PCIe device treepatrick2020-04-231-2/+3
* Remove unnecessary retrieval of the GPC regmap. We don't need it sincepatrick2019-08-261-4/+2
* Change pci_intr_handle_t into a struct and replace duplicated code thatkettenis2019-06-031-85/+20
* Add MSI-X support.kettenis2019-05-311-29/+39
* Add i.MX8MQ support to dwpcie(4). Since the i.MX8MQ does seem topatrick2019-01-111-77/+427
* Initialize bridge registers instead of relying on ppb(4) to do it for us.kettenis2018-08-221-39/+55
* Implement address translation. Makes I/O space access work.kettenis2018-08-211-7/+89
* Give the FDT interrupt API a more generic naming by replacing thepatrick2018-08-061-4/+4
* Pass PCIe requester ID as sideband data here as well.kettenis2018-08-031-1/+3
* Make use of PCI_FLAGS_MSI_ENABLED such that drivers for hardware with brokenkettenis2018-07-281-2/+4
* Use generated string for the bus number extent.kettenis2018-07-011-2/+2
* Implement support for INTx interrupts on Marvell ARMADA 7K & 8K.kettenis2018-04-091-1/+37
* The Open Firmware Interrupt Mapping "recommendation" says that the numberkettenis2018-04-091-3/+2
* Add more initialization code such that things work with the EDK2-basedkettenis2018-04-051-31/+196
* Match on the more specific "marvell,armada8k-pcie" instead of the generickettenis2018-04-031-2/+2
* Add dwpcie(4), a (minimal) driver for the Synopsys Designware PCIe core inkettenis2018-04-021-0/+429
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