| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add RK3308 clocks |   jmatthew | 2020-09-06 | 1 | -1/+571 |
| | | | | | ok kettenis@ | ||||
| * | Add RK3399 audio clocks. |   patrick | 2020-06-11 | 1 | -1/+53 |
| | | | | | ok kettenis@ | ||||
| * | Add RK3328 Crypto/RNG clocks. |   kettenis | 2020-04-08 | 1 | -1/+9 |
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| * | Make it possible to set the VPLL clock frequency and add a few more PLL clock | kettenis | 2020-03-01 | 1 | -1/+13 |
| | | | | | | | frequencies that are needed for HDMI support. ok patrick@ | ||||
| * | Add support for the RK3399's VOP clocks to rkclock(4). | patrick | 2020-02-10 | 1 | -2/+53 |
| | | | | | | | | | | | | | The main VOP DCLK clocks either have a normal divisor as a parent or some fractional one. The clock referred in the device tree to set the frequency on is the mux itself, which has no divisor. To To be able to set the frequency, we need to allow setting it on the parent anyway. Thus move the divisor mask check to a later point, so even though we have no divisor, we can still tell the parent to adjust itself. ok kettenis@ | ||||
| * | delete wasteful ;; |   deraadt | 2020-01-22 | 1 | -2/+2 |
| | | | | | ok tedu | ||||
| * | Add support for the RK3399's PWM clock to rkclock(4). | patrick | 2019-12-03 | 1 | -1/+7 |
| | | | | | ok kurt@ | ||||
| * | Add support for the RK3399's eMMC clock to rkclock(4). | patrick | 2019-11-29 | 1 | -1/+7 |
| | | | | | | Tested by kurt@ ok kettenis@ | ||||
| * | Start using the generic clock code on RK3288 as well by switching over the | kettenis | 2019-09-20 | 1 | -22/+17 |
| | | | | | SDMMC clock. | ||||
| * | Add RK3288 GMAC clock. | kettenis | 2019-09-20 | 1 | -2/+24 |
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| * | More RK3328 GMAC clock tweaking. | kettenis | 2019-09-20 | 1 | -3/+15 |
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| * | Add RK3328 GMAC clocks. | kettenis | 2019-09-19 | 1 | -3/+42 |
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| * | Add RK3399 GMAC clock. | kettenis | 2019-09-16 | 1 | -1/+6 |
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| * | Add some additional RK3399 clocks that are used by the current Linux | kettenis | 2019-01-01 | 1 | -1/+16 |
| | | | | | mainline device tree. | ||||
| * | Add RK3399 TSADC clock. | kettenis | 2019-01-01 | 1 | -1/+8 |
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| * | Add RK3328 TSADC clock. | kettenis | 2019-01-01 | 1 | -1/+11 |
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| * | Implement switching to different parent clocks in order to get as close | kettenis | 2019-01-01 | 1 | -10/+68 |
| | | | | | to the desired frequency as possible when setting the frequency of a clock. | ||||
| * | Make sure we don't exceed the maximum clock divider. | kettenis | 2019-01-01 | 1 | -5/+11 |
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| * | Fix typo in RK3328 fractional PLL frequency code. | kettenis | 2019-01-01 | 1 | -2/+2 |
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| * | Set assigned-clocks on RK3328. | kettenis | 2018-12-31 | 1 | -2/+2 |
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| * | Use data structures for the RK3399 as well. | kettenis | 2018-12-31 | 1 | -361/+173 |
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| * | Implement fractional PLL frequencies for RK3328 and use them for APLL and | kettenis | 2018-12-31 | 1 | -9/+211 |
| | | | | | | | | | | | | GPLL like the Linux kernel does. Use NPLL for the CPU clock such that adjusting the CPU frequency doesn't change the clock of other devices anymore. Implement the last clocks that are used in the assigned-clocks property of clock controller. Don't enable the assigned-clocks processing yet as it results in a sub-optimal clock for for the SD and eMMC controllers. This clock handling in dwmcc(4) needs some further work before we can enable this. | ||||
| * | Revamp the way we handle clocks on the RK3328. Instead of having code for | kettenis | 2018-12-31 | 1 | -177/+245 |
| | | | | | | | | | | | each and every clock, use a data structure for each clock and generic code that handles muxing and clock division based on that data structure. This should reduce the amount of code and hopefully make the process of adding clocks less error prone as it is easy to check the data structures against the SoC documentation. This approach will be used for the other Rockchip SoCs in the future as well. | ||||
| * | More RK3328 clock stuff. | kettenis | 2018-12-30 | 1 | -9/+132 |
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| * | Implement setting CPU-related clocks for RK3328. | kettenis | 2018-12-30 | 1 | -27/+229 |
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| * | Implement a few missing RK3288 clocks and implement resets. | kettenis | 2018-08-04 | 1 | -2/+8 |
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| * | Implement DVFS support. | kettenis | 2018-08-03 | 1 | -27/+1 |
| | | | | | ok patrick@ | ||||
| * | Fix various RK3399 clocks and add support for getting the clock frequency | kettenis | 2018-08-01 | 1 | -23/+100 |
| | | | | | | | | | | | | of the clocks that we can set. Assign clock rates (and parents) based on the "assigned-clocks" device tree property, but only on RK3399 for now as the code for the other Rockchip SoCs isn't quite ready yet. Last but not least, fixup a mistake on the firmware for the Theobroma Systems RK3399-Q7 module such that the "big" cluster uses BPLL as intended. | ||||
| * | Correctly set the dividers for the clock of the "big" cores. | kettenis | 2018-07-31 | 1 | -5/+5 |
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| * | Add more RK3399 clocks such that we can support assigned locks for the | kettenis | 2018-06-02 | 1 | -11/+151 |
| | | | | | clock controller. | ||||
| * | Add code to set the frequency of the SDMMC and SDIO clocks. | kettenis | 2018-06-01 | 1 | -1/+31 |
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| * | Add clocks for RK3399 SDIO controller. | kettenis | 2018-05-26 | 1 | -1/+30 |
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| * | More RK3328 clocks. | kettenis | 2018-02-25 | 1 | -32/+93 |
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| * | Initial RK3328 clocks. | kettenis | 2018-02-25 | 1 | -3/+163 |
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| * | Instead of adding each and every clock to the list of clocks that are enabled | kettenis | 2018-01-03 | 1 | -47/+15 |
| | | | | | by default, simply assume they are. But do check for this when we attach. | ||||
| * | Remove the RK3399-specific cpuspeed implementation as the generic one works | kettenis | 2017-12-29 | 1 | -16/+1 |
| | | | | | fine for this SoC. | ||||
| * | Add support for the CPU clock on the RK3288. Set its frequency to 1.2 GHz | kettenis | 2017-12-29 | 1 | -6/+140 |
| | | | | | on the Tinker-RK3288 such that things run a bit faster. | ||||
| * | Add RK3288 CPU core related clocks. | kettenis | 2017-12-28 | 1 | -1/+10 |
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| * | handle rk3288 i2c clocks |   jsg | 2017-09-02 | 1 | -2/+35 |
| | | | | | with help from kettenis@ | ||||
| * | Add RK3399 i2c-related clocks and fix a typo. | kettenis | 2017-08-27 | 1 | -6/+102 |
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| * | Mark decimal constants as unsigned to avoid gcc warning. | kettenis | 2017-08-26 | 1 | -22/+22 |
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| * | Add supporting for adjusting the CPU core clock frequency on RK3399. | kettenis | 2017-08-26 | 1 | -24/+227 |
| | | | | | | Use this to bump up the clock of the "LITTLE" cluster on the Firefly-RK3399 to 1.2 GHz to make the board a bit more usable. | ||||
| * | Add rktemp(4), a driver for the temperature sensors on the Rockchip RK3399 | kettenis | 2017-08-25 | 1 | -1/+3 |
| | | | | | SoC. | ||||
| * | Slightly rework how the SoC-specific functions are set up and introduce an | kettenis | 2017-08-23 | 1 | -19/+35 |
| | | | | | | | init function such that we can do some SoC-specific setup. Use this function to set cpu_cpuspeed. On (future) MULTIPROCESSOR kernels bump the PLL for the "big" cluster out of slow mode here. | ||||
| * | Add RK3399 CPU core related clocks. Fix RK3399 SD/MMC controller clock. | kettenis | 2017-08-21 | 1 | -5/+73 |
| | | | | | | For now, expose the clock speed of the Cortex-A53 cores through the hw.cupseed sysctl. | ||||
| * | Add RK3399 USB3 related clocks. | kettenis | 2017-08-07 | 1 | -1/+8 |
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| * | Add a few more RK3288 clocks. | kettenis | 2017-07-23 | 1 | -1/+6 |
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| * | Add RK3288 support. | kettenis | 2017-07-23 | 1 | -3/+151 |
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| * | More SD/MMC controller-related clocks. | kettenis | 2017-05-20 | 1 | -1/+33 |
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| * | Add some SD/MMC controller-related clocks. | kettenis | 2017-05-15 | 1 | -1/+32 |
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| WireGuard implementation for the OpenBSD kernel | Matt Dunwoodie |
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