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* PLL1(CPU_PLL) stability improvement for Allwinner H3/H2+uaa2020-08-301-6/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to unstable of PLL1, sometimes the system has hanged up especially at boot. This is observed at Allwinner H3/H2+ processor. To solve the problem, PLL1 setting procedure is same as Linux. 1. change clock source to 24MHz 2. wait 1usec (new) 3. disable PLL1 (new) 4. set new NKMP value, but M should be 1 5. re-enable PLL1 (new) 6. wait PLL1 stable (modified) 7. change clock source to PLL1 8. wait 1usec (new) Once disable PLL1 before setting NKMP is very important. And, sometimes LOCK flag is set even if PLL has not locked yet so wait for PLL is modified with simple delay() by the value of PLL_STABLE_TIME_REG1 register. Not only Allwinner H3/H2+ but also all (i.e. A64) Allwinner processors datasheet has "If the clock source is changed, at most to wait for 8 present running clock cycles." sentence at CPU clock source selection field of CPU/AXI configuration register. But this is ambiguous that _who_ should do _what_ during that cycles. It is unclear that changing clock source itself invoke PLL1 unstability. For safety, added 1usec wait after changing clock source like Linux. ok by kettenis@, thanks to adr at sdf dot org
* Add a few more Allwinner A80 clocks and resets.kettenis2020-03-281-1/+25
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* Implement setting the CPU clock for Allwinner A10/A20 SoCs.kettenis2019-09-211-1/+46
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* Add A20 GMAC clocks.kettenis2019-09-201-2/+15
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* Add Allwinner H6 support.kettenis2019-09-081-5/+133
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* Implement setting the CPU clock for Allwinner A64 SoCs.kettenis2019-09-021-1/+84
| | | | From Krystian Lewandowski.
* Add Allwinner V3s support. From SASANO Takayoshi.kettenis2019-02-121-1/+94
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* Implement setting the CPU clock for Allwinner H3/H5 SoCs.kettenis2018-08-031-1/+50
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* Add 20 MHz MMC clock.kettenis2018-05-271-1/+2
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* On Allwinner R40, export a regmap covering the GMAC_CLK_REG.kettenis2018-05-271-4/+43
| | | | Add a few more R40 clocks needed by the GMAC.
* More Allwinner A64 clocks.kettenis2018-02-101-2/+4
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* Implement H3/H5 CPU clock.kettenis2017-12-311-1/+37
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* Implement Allwinner A40/V40 support.kettenis2017-12-301-1/+53
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* Add support for the PRCM clocks on Allwinner A23/A33.kettenis2017-12-301-15/+24
| | | | Tested by kevlo@
* Add support for the 2nd clock control module on the Allwinner H3/H5.kettenis2017-12-281-1/+59
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* Implement support for the "next-generation" clock bindings for thekevlo2017-12-261-1/+108
| | | | | | Allwinner A23/A33. ok kettenis@
* Implement A10/A20 CPU clock.kettenis2017-12-241-12/+55
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* Add a few more Allwinner A80 clocks.kettenis2017-12-151-1/+44
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* Add more Allwinner A80 clocks.kettenis2017-12-121-19/+60
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* Implement support for the "next-generation" clock bindings for thekettenis2017-12-111-10/+59
| | | | Allwinner A80.
* Implement support for the "next-generation" clock bindings for thekettenis2017-11-191-3/+57
| | | | Allwinner A10/A20.
* If you use sys/param.h, you don't need sys/types.hderaadt2017-09-081-2/+1
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* Support Allwinner A64's ethernet controller clocks and resetpatrick2017-09-021-1/+44
| | | | | | | based on the H3 code which is essentially the same apart from differing device tree indices. ok phessler@
* fix previous to make sxiccmu compile againjsg2017-07-181-2/+2
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* The Linux kernel device trees use "allwinner,sun50i-h5-ccu" as the compatiblekettenis2017-07-171-7/+9
| | | | | propert for the clock controller module. Prepare for the day when the u-boot device trees get update.
* Match /clocks node on Allwinner H5.kettenis2017-07-161-1/+2
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* Add support for a few more Allwinner H3 clocks.kettenis2017-03-261-14/+72
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* Move Allwinner drivers that will soon be used by OpenBSD/arm64patrick2017-01-211-0/+792
to the new MI FDT driver directory. "go ahead" kettenis@
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