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* Clean up nonexistent/unused properties handlingkn2021-04-011-12/+1
* Hardcode meaningful alert level, track apm's battery state betterkn2021-04-011-23/+7
* Flag sensors as invalid on bogus readskn2021-03-261-3/+7
* Provide apm(4/arm64) with battery informationkn2021-03-251-1/+41
* Load MSI pages through bus_dma(9). Our interrupt controllers for MSIspatrick2021-03-221-4/+53
* Update device-tree bindingskn2021-03-221-6/+6
* Advertise 30-bit color support.kettenis2021-03-131-2/+5
* Make sure to skip attaching disabled I2C devices. This can happen onpatrick2021-03-115-10/+35
* Make sure to skip attaching disabled I2C devices. This can happen onpatrick2021-03-111-2/+7
* Add support for 30-bit color modes.kettenis2021-03-091-2/+4
* Add support for rk809 as seen on the Rock Pi N10 with the rk3399pro. Addkurt2021-03-081-57/+262
* Transactions on the AXI bus contain a Stream ID. SMMUs filterpatrick2021-03-011-1/+15
* The ep-gpios property is optional on the Rockchip PCIe controller.patrick2021-03-011-11/+21
* Issue call to IOMMU OFW API to collect an IOMMU-sprinkled DMA tag.patrick2021-02-281-1/+7
* Add some infrastructure in the PCI chipset tag for pci_probe_device_hook()patrick2021-02-254-4/+36
* Disable double-data rate modes if 1.8V signalling is not possible.patrick2021-02-221-2/+4
* Slow mode is only relevant for legacy and high speed timings.patrick2021-02-221-3/+3
* Improve support for the variant found on the Apple M1 SoC.kettenis2021-02-222-64/+161
* Add support for the UART found on the Apple M1 SoC.kettenis2021-02-162-10/+30
* Introduce variables to deal with bit layout differences in the UFSTATkettenis2021-02-141-9/+26
* Don't hardcode com(4)'s major number in exuart(4).patrick2021-02-111-5/+12
* arm_intr_establish_fdt() has long been renamed to fdt_intr_establish().patrick2021-02-053-8/+7
* Fix CVS tag.patrick2021-02-051-1/+1
* Fix whitespace.patrick2021-02-051-2/+2
* Rename probe/attach functions to fit our regular naming scheme. Replacepatrick2021-02-051-13/+13
* Move exuart(4) to sys/dev/fdt so it can be shared between arm64 and armv7.patrick2021-02-053-1/+1057
* Tedu unnecessary imxuartvar.h.patrick2021-02-042-21/+1
* handle #pinctrl-cells 2jsg2021-02-011-2/+7
* Reprogram outbound windows to match the device tree. Necessary becausekettenis2021-01-201-3/+34
* Implement intx support.kettenis2021-01-191-19/+123
* Handle pinctrl.kettenis2020-12-291-1/+4
* Add more PWM pin descriptions.kettenis2020-12-291-1/+32
* Add support for the PCIe controller found on Amlogic G12A/G12B/SM1 SoCs.kettenis2020-12-281-11/+119
* Remove debug printf.kettenis2020-12-271-2/+1
* Add PCIe support.kettenis2020-12-271-48/+68
* Add PCIe power domain.kettenis2020-12-271-1/+14
* Add PCIe clocks.kettenis2020-12-221-1/+5
* Defer hardware initialization in order to give things like PCIe PHYskettenis2020-12-221-15/+31
* There's no need to include the OFW GPIO header.patrick2020-12-191-2/+1
* Add support for the i.MX8MP PCIe clocks.patrick2020-12-192-1/+40
* Add support for the i.MX8MP second ethernet. The Plus SoC not only has thepatrick2020-12-182-4/+98
* Emulate open drain GPIOs. This replaces the hack added in the last commit.kettenis2020-12-181-31/+22
* Make large read and write transactions work.kettenis2020-12-181-39/+59
* Add glue for the USB3 controller on the i.MX8MP SoC. NXP had this glue forpatrick2020-12-182-1/+80
* Add code to initialize the USB 3 PHY on i.MX8MP.patrick2020-12-181-2/+65
* Add support for the i.MX8MP USB clocks.patrick2020-12-182-2/+88
* Attach imxgpc(4) to i.MX8MP as well.patrick2020-12-181-1/+3
* Only enable the USB 3.0 port and PHY if it is enabled on a board.kettenis2020-12-171-5/+7
* Reset pin 3 of the GPIOAO bank to input mode to work around a hardwarekettenis2020-12-171-2/+31
* Match on "amlogic,meson-g12a-dwmac" which is used by newer Linux mainlinekettenis2020-12-171-1/+2
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