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* Turning on various scsi drivers' *DEBUG options reveals that this haskrw2020-07-241-3/+3
| | | | | | | | rarely (if ever) been done. Fix many printf format errors to calm clang and gcc on amd64, i386, hppa. Missing #include, complaints if 'option <blah>DEBUG' is used in config files, etc. All in debug code.
* remove some ifdef notyet code that doesn't seem to be moving forward...tedu2020-01-241-249/+1
| | | | some ok ratchov
* consistently uppercase pci product definesjsg2020-01-051-3/+3
| | | | ok mpi@
* Introduce two quirks to prevent attaching ATA and ATAPI devicesmikeb2017-07-121-1/+9
| | | | | | | | | Hyper-V and Xen have varying support for detaching emulated IDE devices ranging from none on Hyper-V to only IDE disks but not CDROM (Xen). The quirk mechanism provides a way of enforcing the desired behavior. With suggestions and OK kettenis, tedu, mlarkin
* Goto a loop_end label rather than using a continue statement for anmmcc2015-12-211-2/+4
| | | | | | error condition in an inner loop. Found with Coccinelle. Pointed out by tedu@, ok kettenis@ and deraadt@ about three months ago.
* Double the delay between the PHY reset and the status check formpi2015-11-241-2/+2
| | | | | | | | ServerWorks SATA. Allow to reliably found disks on xserve G5. from miod@
* The change of 5.7's sys/arch/i386/i386/bus_space.c anduaa2015-10-181-2/+14
| | | | | | | | | | | | | | | | | | | | sys/arch/i386/include/bus.h invokes the kernel crash at boot when ignored (disabled) channel is detected. In all ATA controllers, ignored (disabled) channel is still set cp->hwok = 1. And pciide_mapregs_native() is not called, wdc_cp->cmd_iot is 0. 5.6 and before, cmd_iot = 0 is treated as I386_BUS_SPACE_IO, so there is no problem to call bus_space_read_1() in wdcintr(). 5.7 and after, cmd_iot is used as function pointer. We have to initialize it with pciide_mapregs_native() or something, otherwise set cp->hwok = 0 to prevent calling wdcintr(). When ignored (disabled) channel is found, default_chip_map() should set cp->hwok = 0. So all controllers do same thing. ok by deraadt@
* sizes for free(); ok sthenderaadt2015-09-101-8/+14
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* Print speeds consistently.mpi2015-03-211-10/+10
| | | | ok brynet@, miod@
* Remove some includes include-what-you-use claims don'tjsg2015-03-141-2/+1
| | | | | | | have any direct symbols used. Tested for indirect use by compiling amd64/i386/sparc64 kernels. ok tedu@ deraadt@
* match on C610jsg2015-01-091-1/+13
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* Use <sys/endian.h> instead of <machine/endian.h>guenther2014-12-191-2/+2
| | | | ok dlg@ mpi@ bcook@ millert@ miod@
* Additonal registers needs to be saved in sc_save2, not sc_save.kettenis2014-10-161-5/+5
| | | | ok deraadt@
* match on Intel 9 series and 9 series LP PCH, and add 8 series KT to pucjsg2014-08-131-1/+9
| | | | ok millert@
* pciide.c, pciide_rdc_reg.h(new): ported rdcide(4) from NetBSD.sasano2014-07-131-2/+163
| | | | | | | | it supports RDC's R1012 IDE controller. tested on 86duino EduCake (DM&P Vortex86EX SoC) ok by deraadt@
* add a size argument to free. will be used soon, but for now default to 0.tedu2014-07-121-2/+2
| | | | after discussions with beck deraadt kettenis.
* no need to check for default_chip_map twice in one if statementjsg2014-04-241-2/+1
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* match some more intel sata devices in ide modejsg2014-04-241-1/+73
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* Add a DVACT_WAKEUP op to the *_activate() API. This is called after thederaadt2013-12-061-7/+4
| | | | | | | | kernel resumes normal (non-cold, able to run processes, etc) operation. Previously we were relying on specific DVACT_RESUME op's in drivers creating callback/threads themselves, but that has become too common, indicating the need for a built-in mechanism. ok dlg kettenis, tested by a sufficient amount of people
* Fix edge cases of uninitialized variables. In my tree for too long, I evenmiod2013-05-271-1/+2
| | | | got ok's for azalia but I don't remember from whom.
* - add some intel 7 series sata ids.jasper2013-01-051-1/+13
| | | | ok jsg@
* Revamp the sequences for suspend/hibernate -> resume so that the codederaadt2012-10-081-1/+4
| | | | | | | | | | paths are reflexive. It is now possible to fail part-way through a suspend sequence, and recover along the resume code path. Split DVACT_SUSPEND by adding a new DVACT_POWERDOWN method is used after hibernate (and suspend too) to finish the job. Some drivers must be converted at the same time to use this instead of shutdown hooks (the others will follow at a later time) ok kettenis mlarkin
* VT6410 and VT6415 controllers do not implement the `channel enable' register,miod2012-04-221-17/+27
| | | | | | so don't incorrectly assume both channels are disabled on these controllers. ok jsg@
* Don't call wdcintr() for channels that aren't properly initialized or don'tkettenis2012-03-131-1/+4
| | | | | | | have any drives on them. Fixes a panic seen on sparc64 machines with that pesky Acer Labs chipset. ok deraadt@, krw@, henning@
* As SiS IDE has the same PCI product id for different revisionsjsg2012-01-151-2/+4
| | | | | | | with different bugs the host bridge is used to determine which path to take. As pointed out by Chris Cappuccio we need to expand this list to cover newer chips SiS have inflicted on the world. From and tested by Loganaden Velvindron (on SiS 968).
* Add support for SiS 1183 SATA. From/tested by Loganaden Velvindron.jsg2012-01-041-1/+5
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* Unbreak tree after kettenis's sanitization in pcidevsguenther2011-11-121-9/+9
| | | | ok krw@
* Make sure we set UDMA capabilities for HT-1000 IDE,jsg2011-11-021-1/+2
| | | | | this was missed when support for HT-1000 IDE was added. From Brad.
* use default_chip_unmap for sata_chip_map, lets the via controllers detachjsg2011-09-171-1/+2
| | | | ok deraadt@
* Cope with the start-dma-before-init errata and some other register setupderaadt2011-07-151-1/+12
| | | | | errata for the Serverworks SATA chipset found on the macppc xserve G5. ok jmc
* pass the interface for non-compat-mode piix. from netbsd.jcs2011-07-111-7/+6
| | | | ok deraadt@ jsg@
* Refactor queue allocation and initialization into a wdc_alloc_queue()matthew2011-05-091-20/+14
| | | | | | | | | | | function, and let attachment code calls this rather than malloc(9). This prevents re-initialization of the queue in shared queue chipsets. Also, add wdc_free_queue() as a complementary function. Earlier version (without wdc_free_queue()) tested by sthen@ and Amit Kulkarni on various pciide(4) chips. ok dlg@
* Initialize the wdc ata_drive_datas structs earlier in wdcattach() somatthew2011-05-091-22/+4
| | | | | | | | | that chip-specific drv_probe routines can assume they've already been initialized. Tested by sthen@ on i386, armish, and amd64, with both affected and non-affected pciide(4) chips. ok dlg@
* support Intel 6 series SATA in non raid/non ahci mode.jsg2011-04-271-1/+17
| | | | tested by Daniel Dickman
* keep an eye out for wdc registers returning 0xff. if they return 0xff,deraadt2011-04-181-1/+3
| | | | | | | | this probably means the controller is dead -- as in, a hot plug eject event. in that case, mark the driver dead and try harder to return -1 in the interrupt handler. tested by many ok dlg, miod did not object
* add support for VIA VT6415 & VX900 IDEjsg2011-04-141-2/+12
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* Avoid using an uninitialized variable when downgrading PIO mode too much onmiod2011-04-071-1/+2
| | | | ITExpress chipsets. (similar to 1.243, with a deja vu)
* use nitems(); no binary change for drivers that are compiled on amd64.jasper2011-04-031-23/+21
| | | | ok claudio@
* Mark NVIDIA MCP89 SATA controllers as such. Makes them use DMA instead of PIOkettenis2010-11-181-1/+17
| | | | | | such that we get decent performance out of them. ok jsg@
* Revision 0xc4 and earlier of the Acer Labs M5229 UDMA IDE controller can't dokettenis2010-11-061-1/+15
| | | | | | | | | | DMA for LBA48 commands. Work around this issue by (silently) falling back to PIO for LBA48 commands. Access to the tail end of large disks will be much slower, but at least it works. From NetBSD (Takeshi Nakayama). ok jsg@, krw@, deraadt@
* Add DVACT_QUIECE support. This is called before splhigh() and beforederaadt2010-08-311-1/+4
| | | | | | | | DVACT_SUSPEND, therefore DVACT_QUIECE can do standard sleeping operations to get ready. Discussed quite a while back with kettenis and jakemsr, oga suddenly needed it as well and wrote half of it, so it was time to finish it. proofread by miod.
* no need to specially handle the 4 AMD756 registers at suspend/resume time;deraadt2010-08-311-19/+2
| | | | | they fall within the pcipower() handled range. ok miod
* PCI configuration space register save/restore for AMD756.miod2010-08-311-1/+19
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* ok, that is the last of the easy chips to check for register saves. i'mderaadt2010-08-061-2/+3
| | | | | going to give up on reading gobs of crap for a while and hope that someone else takes on the next few.
* another set of chips which do not need register rewrites at resume timederaadt2010-08-061-1/+2
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* no special registers to restore on via chips eitherderaadt2010-08-031-2/+3
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* jmicron code was writing to the wrong register; ok jsgderaadt2010-08-021-2/+2
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* Save/restore more registers at suspend/resume for those chips which lookderaadt2010-08-021-9/+28
| | | | like they need it. (Or don't, when it appears they don't need it)
* the default pciide chip needs no additional register restores; tested by jcs on one modelderaadt2010-07-281-2/+4
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* suspend save/restore for SIS3112; tested by mlarkinderaadt2010-07-281-1/+13
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