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* Register the PCI variant of dwiic(4) with acpi(4).kettenis2021-03-301-2/+7
| | | | ok tb@
* Move tx/rx descriptors into their own structs.kevlo2021-03-302-188/+509
| | | | | | | | | This is a first step toward making rge work with multiple queues and interrupts. Only one queue is currently used. While here, update the RTL8125B microcode. ok jmatthew@
* Since ipw(4) doesn't call into net80211_newstate() the interface link statestsp2021-03-281-1/+13
| | | | | | | | | must be updated by the driver in order to get packets to flow. In case of WPA the link state was updated as a side-effect of a successful WPA handshake. This commit fixes the WEP and plaintext cases. Problem reported and fix tested by Riccardo Mottola.
* regenjan2021-03-261-1/+5
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* Add PCI ID for Intel X710 10G SFP+ NICjan2021-03-261-1/+2
| | | | ok patrick@
* regenjan2021-03-261-1/+2
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* Add missing PCI ID for Intel X710 SFP+ NICjan2021-03-261-1/+2
| | | | ok patrick@
* Let iwn(4) simply clear frames before the firmware's BA window, insteadstsp2021-03-221-29/+17
| | | | | | | | | | | | | | | | of trying to be smart and clearing already acknowledged frames which are still within the firmware's BA window. This matches what the Linux driver does and makes our driver code simpler. Also, Tx rate control code relies on sequence numbers falling into the BA window so let's skip Tx rate control for frames before this window. Tested by: myself on 6205 and 6300 afresh1, bluhm, and paco on 6300 jmatthew on 5100 Balder Oddson on 6205
* Make iwx(4) attach to AX201 devices with PCI ID 0x34f0.stsp2021-03-171-1/+14
| | | | | | Requires Qu-c0-hr-b0-48 firmware which is available via fw_update(1). Patch by Fredrik Engberg
* regenstsp2021-03-172-2/+7
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* Add another iwx(4) PCI device ID.stsp2021-03-171-1/+2
| | | | Based on a patch by Fredrik Engberg
* Make iwn(4) send block ack request frames with the firmware nodestsp2021-03-171-2/+5
| | | | | | | | | | | which represents the AP, rather than the firmware's broadcast node. Fixes a problem where firmware would generate bogus block ack requests with a wrong starting sequence number, shifting the receiver's block ack window out of sync with that of the firmware. Traffic would stall until enough frames were sent to wrap sequence numbers of the block ack window. ok chris@ kmos@
* regenjan2021-03-142-2/+7
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* Add ID for Intel SSD DCjan2021-03-141-1/+2
| | | | ok jsg@
* In ipw(4), ensure that net80211 is in ASSOC state while we are expectingstsp2021-03-121-1/+7
| | | | | | | | an assoc response from the AP during the association sequence. Otherwise net80211 would ignore the auth response, resulting in a state mismatch between firmware and net80211. A symptom of this was that WPA didn't work. Problem reported and fix tested by Ricardo Mottola
* Use RA instead of MiRA in iwn(4).stsp2021-03-122-191/+129
| | | | | | | Tested by: iwn 6200: stsp iwn 6205: cwen, Jeremy O'Brien iwn 6300: okan
* Use RA instead of MiRA in iwm(4).stsp2021-03-122-49/+66
| | | | | | | | | | | Tested by: iwm 7260: florian iwm 7265: TronDD, Aaron Miller, stsp iwm 8260: bket iwm 8265: matthieu, tracey, naddy, Dave Voutila, jcs, Mathieu Kerjouan, Matthias Schmidt, stsp iwm 9260: matthieu, phessler, Darren VanBuren iwm 9560: Uwe Werler
* ansijsg2021-03-0515-250/+113
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* regenjsg2021-02-272-14/+14
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* sortjsg2021-02-271-5/+5
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* regenjsg2021-02-272-32/+312
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* add ids for Intel Xeon Scalablejsg2021-02-271-7/+63
| | | | | | | | | | | | | | | Used by at least Skylake-SP (SKX) and Cascade Lake-SP (CLX). Covers Xeon Scalable, Xeon D, Xeon W, Core Extreme/Core X product families. The Scalable parts are marketed as Xeon Bronze, Silver, Gold and Platinum. As most of these ids are not described in public documents from Intel use Skylake-ESystem.inf and KabyLakePCH-HSystem.inf from Intel's Windows drivers to get an idea of what the names should be. With the name for 0x2088 found in a Intel authored Linux driver. Initial patch and much discussion from Karel Gardas.
* Read and parse OTP on the BCM4378. There are quite a few firmware andpatrick2021-02-261-1/+133
| | | | | | | nvram files used for the different Apple devices. The device tree and the OTP hold the information which of those we will have to use. For now this information will simply be printed, but depending on how we choose to do the firmare distribution we could use it for loadfirmware().
* Attach to BCM4378.patrick2021-02-261-1/+2
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* Add support for BCM4378 as implemented on the Apple M1. This chip seemspatrick2021-02-262-26/+126
| | | | | | | | to use a different set of PCIE2REG registers. Accessing the "old" ones even leads to faults. There are two surprises though. One is that it seems that the interrupt status register always returns 0, and the other one is that we receive the interrupts way too early, but both can be worked around for now.
* touch pcidevs again to generated new rcs ids in headersjan2021-02-262-2/+2
| | | | advince from sthen@
* Increase the amount of RX buffers given to the bwfm(4) chip. We haave seenpatrick2021-02-261-4/+4
| | | | | | this already on previous chips, which only started giving us packets when handing over at least 128 of them. Apparently some now require 256, which seems to get the Apple M1's WiFi going.
* Add missing PCI product IDs for x710 10GBase-T into ixl(4)jan2021-02-264-2/+9
| | | | OK phessler
* Increase the buffer size for the ioctl response buffers to the same aspatrick2021-02-262-7/+8
| | | | used in the wifi firmware to ensure responses can be received.
* Indicate hostready signal to inform the firmware that the rings have beenpatrick2021-02-262-4/+18
| | | | initialized.
* Refactor bwfm(4) firmware loading. The PCIe backend will need to be ablepatrick2021-02-261-28/+5
| | | | | | | to load the CLM blob like the SDIO backend already does. Additionally it is also helpful for the PCIe backend to try a file named after the device tree compatible. Thus refactor the SDIO code and make it available for both SDIO and PCIe.
* Fix prio2fifo mapping table.patrick2021-02-261-5/+5
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* The firmware replaces the last 32-bit on RAM with a shared DRAM address.patrick2021-02-251-2/+8
| | | | | | | While the for-loop checks that thie value has changed since we wrote to it, the timeout-condition checked for non-zero, which is wrong. This means that we didn't realize the firmware wasn't started. While there, make sure the shared DRAM address is inside the chip's address space.
* Some newer chips have two D11/802.11 cores, and we need to reset both atpatrick2021-02-251-2/+2
| | | | the same time.
* Support for version 7 of the bwfm(4) PCIe interface. The size of the itemspatrick2021-02-252-5/+7
| | | | | on the rx/tx complete rings has increased slightly to accomodate possible new features.
* we don't have to cast to caddr_t when calling m_copydata anymore.dlg2021-02-254-9/+9
| | | | | | | | | | | | | | | | the first cut of this diff was made with coccinelle using this spatch: @rule@ type caddr_t; expression m, off, len, cp; @@ -m_copydata(m, off, len, (caddr_t)cp) +m_copydata(m, off, len, cp) i had fix it's opinionated idea of formatting by hand though, so i'm not sure it was worth it. ok deraadt@ bluhm@
* remove some unused includesjsg2021-02-232-657/+0
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* timecounting: use C99-style initialization for all timecounter structscheloha2021-02-232-18/+18
| | | | | | | | | | | | | | | | | | The timecounter struct is large and I think it may change in the future. Changing it later will be easier if we use C99-style initialization for all timecounter structs. It also makes reading the code a bit easier. For reasons I cannot explain, switching to C99-style initialization sometimes changes the hash of the resulting object file, even though the resulting struct should be the same. So there is a binary change here, but only sometimes. No behavior should change in either case. I can't compile-test this everywhere but I have been staring at the diff for days now and I'm relatively confident this will not break compilation. Fingers crossed. ok gnezdo@
* regenjsg2021-02-222-8/+120
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* add some AMD 500 series, 17h/71h, Navi 10 and Kingston NVMe idsjsg2021-02-221-4/+28
| | | | initial diff from Sven Wolf
* remove warning about amdgpu userptr ioctl being unimplementedjsg2021-02-201-1/+0
| | | | | matches radeon and i915 reported by Benjamin Baier
* move the rearming of the cq after the refill of the rq.dlg2021-02-151-4/+5
| | | | | | | | this is the only real diff we have left outstanding on a box that experienced rx lockups. since adding this change it's been happy for the last 4 weeks and counting so far. ok jmatthew@
* regenkettenis2021-02-142-2/+12
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* Add a few more devices that show up on the Apple M1 mini.kettenis2021-02-141-1/+3
| | | | ok patrick@, deraadt@
* correct drm work flush behaviourjsg2021-02-142-6/+10
| | | | | | | | | Don't set taskq to system_wq in INIT_WORK(). Test if taskq pointer is non-NULL before calling taskq_barrier() in flush functions. fixes a black screen on boot problem with 5.10.y drm using nano x1 bisected by jcs@ to 'drm/i915: Always flush the active worker before returning from the wait'
* Add missing break in switch statement of rge_activate().stsp2021-02-111-1/+2
| | | | | | | CID 1501716 ok kevlo@ and mestre@ had the same diff
* Simplify sleep_setup API to two operations in preparation for splittingmpi2021-02-082-9/+7
| | | | | | | | | | | | the SCHED_LOCK(). Putting a thread on a sleep queue is reduce to the following: sleep_setup(); /* check condition or release lock */ sleep_finish(); Previous version ok cheloha@, jmatthew@, ok claudio@
* Add basic support for BCM4378 as found on the Apple M1 SoCs. There's apatrick2021-01-311-1/+4
| | | | little bit more to do though before it can be enabled.
* regenpatrick2021-01-312-2/+7
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* Add Broadcom BCM4378.patrick2021-01-311-1/+2
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