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2020-07-21arm64: dts: amlogic: meson-gx: add the Mali-450 OPP table and use DVFSMartin Blumenstingl1-40/+11
Add the OPP table for the Mali-450 GPU and drop the hardcoded initial clock configuration. This enables GPU DVFS and thus saves power when the GPU is not in use while still being able switch to a higher clock on demand. Set the GP0_PLL clock to 744MHz (which is the only frequency which cannot be derived from the FCLK dividers) as the clock driver avoids setting the parent clock rates so the MPLL clocks aren't changed (as these are reserved for audio). The only exception to this is the GXL S805X package because the 744MHz OPP isn't working correctly there. While here, make most of meson-gxl-mali re-usable to reduce the amount of duplicate code between GXBB and GXL. This is more important now as we don't want to duplicate the GPU OPP table. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Link: https://lore.kernel.org/r/20200719173213.639540-2-martin.blumenstingl@googlemail.com
2020-07-13arm64: dts: amlogic: Add the Ethernet "timing-adjustment" clockMartin Blumenstingl1-2/+3
Add the "timing-adjustment" clock now that we know how it is connected to the PRG_ETHERNET registers. It is used internally to generate the RGMII RX delay on the MAC side (if needed). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200620162347.26159-1-martin.blumenstingl@googlemail.com
2020-07-13arm64: dts: meson-gx: Switch to the meson-ee-pwrc bindingsMartin Blumenstingl1-2/+5
The "amlogic,meson-gx-pwrc-vpu" binding only supports the VPU power domain, while actually there are more power domains behind that set of registers. Switch to the new bindings so we can add more power domains as needed. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20200620161211.23685-1-martin.blumenstingl@googlemail.com
2020-05-19arm64: dts: meson-gx: add aiu supportJerome Brunet1-0/+23
Add the AIU audio device to the Amlogic GX SoC family DT. ATM, this device provides the i2s and spdif output stages and also the hdmi and internal codec glues. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com> Tested-by: Christian Hewitt <christianshewitt@gmail.com> Link: https://lore.kernel.org/r/20200421163935.775935-3-jbrunet@baylibre.com
2019-08-09arm64: dts: meson: add video decoder entriesMaxime Jourdan1-0/+11
This enables the video decoder for GXBB, GXL and GXM chips Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-05-21arm64: dts: meson: fix mmc pin biasJerome Brunet1-10/+25
Clk pin does not require bias, data strobe should be pulled low. The rest of the pin (data and cmd) are pulled up. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2019-01-17arm64: dts: meson-gx: add support for simplefbMaxime Jourdan1-0/+6
SimpleFB allows transferring a framebuffer from the firmware/bootloader to the kernel, while making sure the related clocks and power supplies stay enabled. Add nodes for CVBS and HDMI Simple Framebuffers. Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-12-04arm64: dts: meson: add clock controller clock inputsJerome Brunet1-0/+4
Add the clock inputs of the clock controllers Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-29arm64: dts: meson: consistently disable pin biasJerome Brunet1-0/+47
On Amlogic chipsets, the bias set through pinconf applies to the pad itself, not only the GPIO function. This means that even when we change the function of the pad from GPIO to anything else, the bias previously set still applies. As we have seen with the eMMC, depending on the bias type and the function, it may trigger problems. The underlying issue is that we inherit whatever was left by previous user of the pad (pinconf, u-boot or the ROM code). As a consequence, the actual setup we will get is undefined. There is nothing mentioned in the documentation about pad bias and pinmux function, however leaving it undefined is not an option. This change consistently disable the pad bias for every pinmux functions. It seems to work well, we can only assume that the necessary bias (if any) is already provided by the pin function itself. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-29arm64: dts: meson: disable pad bias for mmc pinmuxesJerome Brunet1-0/+4
In some cases (such as a boot from SPI) the bootloader or the ROM code may leave a bias pull-down on the mmc pins. If so the MMC will fail during the initialisation. Explicitly disabling the pinmux solves the problem. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-29arm64: dts: meson: remove extra subnode in mmc clk_gate pinmuxJerome Brunet1-9/+0
In the pinmux of the mmc clk_gate nodes, we define 2 subnodes. One for the function definition, the other for the bias. This is not necessary since we can define the function and the bias in the same subnode. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-11-15arm64: dts: meson-gx: add efuse pclkJerome Brunet1-0/+4
Add the required peripheral clock for the efuse device. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-09-14arm64: dts: meson: Fix erroneous SPI bus warningsRob Herring1-1/+1
dtc has new checks for SPI buses. The meson dts files have a node named spi' which causes false positive warnings. As the node is a pinctrl child node, change the node name to be 'spi-pins' to fix the warnings. arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dtb: Warning (spi_bus_bridge): /soc/periphs@c8834000/pinctrl@4b0/spi: incorrect #address-cells for SPI bus Cc: Carlo Caione <carlo@caione.org> Cc: Kevin Hilman <khilman@baylibre.com> Cc: linux-amlogic@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-05-23ARM64: dts: meson: fix clock source of the pclk for UART_AOYixun Lan1-2/+2
>From the hardware perspective, the actual pclk of the AO uarts is the corresponding clkc_ao uart gate, not the main clock controller clk81. This was not problem so far, because the uart_gate had the CLK_IGNORE_UNUSED flag, which kept the gate open. We plan to remove the CLK_IGNORE_UNUSED flag in another patch, but before doing that, we need to fix the clock in the DTS file. Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-05-09ARM64: dts: meson: add MMC resetsJerome Brunet1-0/+3
Add reset lines to the mmc controllers of the meson gx and axg SoCs Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-04-19ARM64: dts: meson-gx: sysctrl is the parent of the clock controllerJerome Brunet1-3/+2
The parent of the meson-gx clock controller should be the hhi system controller, not the HIU bus. This way, the HHI register region can be used safely by multiple drivers Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-03-19ARM64: dts: meson: bump mali450 clk to 744MHzNeil Armstrong1-4/+7
The Mali-450 IP can run up to 744MHz, bump the frequency using the GP0 PLL clock. Cc: Michal Lazo <michal.lazo@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2018-03-07ARM64: dts: amlogic: Convert to new-style SPDX license identifiersNeil Armstrong1-38/+1
Move the SPDX-License-Identifier lines to the top and drop the license splat. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-12-21Merge tag 'amlogic-dt64' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dtArnd Bergmann1-2/+44
Pull "Amlogic 64-bit DT updates for v4.16" from Kevin Hilman - meson-gx: add VPU power domain support - odroid-c2: add HDMI and CEC nodes - misc cleanups * tag 'amlogic-dt64' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM64: dts: meson-gxm: fix q200 interrupt number ARM64: dts: meson-gxm: add the PHY interrupt line on Khadas VIM2 ARM64: dts: meson: add comments with the GPIO for the PHY interrupts ARM64: dts: amlogic: use generic bus node names ARM64: dts: meson: drop "sana" clock from SAR ADC ARM64: dts: odroid-c2: Add HDMI and CEC Nodes ARM64: dts: meson-gx: grow reset controller memory zone ARM64: dts: meson-gx: Add HDMI_5V regulator on selected boards ARM64: dts: meson-gx: add VPU power domain
2017-12-08ARM64: dts: meson-gx: fix UART pclk clock nameNeil Armstrong1-2/+2
The clock-names for pclk was wrongly set to "core", but the bindings specifies "pclk". This was not cathed until the legacy non-documented bindings were removed. Reported-by: Andreas Färber <afaerber@suse.de> Fixes: f72d6f6037b7 ("ARM64: dts: meson-gx: use stable UART bindings with correct gate clock") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-12-06ARM64: dts: meson: drop "sana" clock from SAR ADCXingyu Chen1-2/+1
The SAR ADC modules doesn't require The "sana" clock. Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Singed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-12-06ARM64: dts: meson-gx: add VPU power domainNeil Armstrong1-0/+43
This patch adds support for the VPU Power Domain nodes, and attaches the VPU power domain to the VPU node. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-29ARM64: dts: meson-gx: add gpio interrupt controllerJerome Brunet1-0/+6
Add gpio interrupt controller to Amlogic GX family SoCs Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-11ARM64: dts: meson-gxl: Take eMMC data strobe out of eMMC pinsNeil Armstrong1-2/+8
Since the Data Strobe pin is optional, take it out of the default eMMC pins and add a separate entry. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-11ARM64: dts: meson-gx: adjust gpio-ranges for TEST_NJerome Brunet1-1/+1
TEST_N has moved from the EE controller to the AO controller so the gpio-ranges need to adjusted for it Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-10-11ARM64: dts: meson-gx: remove gpio offsetJerome Brunet1-1/+1
Remove pin offset on the EE controller. Meson pinctrl no longer has this quirk Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-09-05ARM64: dts: meson: add mmc clk gate pinsJerome Brunet1-0/+33
Add the pinctrl to switch mmc clk pins in gpio (pulled down) mode. This is necessary to be able to gate the clk outside of the SoC while keeping it running in the controller Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-09-05ARM64: dts: meson-gx: Use correct mmc clock source 0Jerome Brunet1-3/+3
Now that the clock source 0 is properly described in the CCF, use it instead of assuming the default value (xtal) Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-08-22ARM64: dts: meson-gx: Add AO CEC nodesNeil Armstrong1-0/+5
This patch adds the AO CEC node in all the HDMI enabled boards DTS. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-08-22ARM64: dts: meson-gx: update AO clkc to new bindingsNeil Armstrong1-0/+4
The AO clkc needs to be updated to new bindings with an system control parent node and moving the clkc node as subnode. Also adds the SoC specific compatible following the bindings requirements. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-08-08ARM64: dts: meson-gx: use stable UART bindings with correct gate clockHelmut Klein1-0/+25
This patch switches to the stable UART bindings but also add the correct gate clock to the non-AO UART nodes for GXBB and GXL SoCs. Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Helmut Klein <hgkr.klein@gmail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-06-16ARM64: dts: meson-gx: Add SPICC nodesNeil Armstrong1-0/+7
Add nodes for the SPICC controller on GX common dtsi, GXBB and GXL dtsi files. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-05-30ARM64: dts: meson-gxbb: Add SPI pinctrl nodesNeil Armstrong1-0/+16
This patch adds the SPICC Controller pins nodes for Amlogic GXBB SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-05-30ARM64: dts: meson-gxbb: Add CEC pins nodesNeil Armstrong1-0/+14
Add the AO and EE domain CEC pins nodes for the Amlogic Meson GXBB SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-05-30ARM64: dts: Fix GXBB periphs pinctrl pull-enable register baseNeil Armstrong1-1/+1
The pull-enable register base was wrongly copied from the meson8b pinctrl node, but was not used yet. Fixes: c328666d58aa ("ARM64: dts: amlogic: Add Meson GX dtsi from GXBB") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-05-17arm64: dts: meson-gxbb: Fix node orderAndreas Färber1-85/+96
Sort nodes referenced by label alphabetically. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-05-09Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-socLinus Torvalds1-32/+140
Pull ARM 64-bit DT updates from Olof Johansson: "Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch of smaller changes, but also some new platforms that are worth mentioning: - Rockchip RK3399 platforms for Chromebooks, including Samsung Chromebook Plus (Kevin) - Orange Pi PC2 (Allwinner H5) - Freescale LS2088A and LS1088A SoCs - Expanded support for Nvidia Tegra186 (and Jetson TX2)" * tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (180 commits) arm64: dts: Add basic DT to support Spreadtrum's SP9860G arm64: dts: exynos: Use - instead of @ for DT OPP entries arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board arm64: dts: juno: add information about L1 and L2 caches arm64: dts: juno: fix few unit address format warnings arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB arm64: marvell: dts: add crypto engine description for 7k/8k arm64: dts: marvell: add sdhci support for Armada 7K/8K arm64: dts: marvell: add eMMC support for Armada 37xx arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board arm64: dts: hisi: add SAS nodes for the hip07 SoC arm64: dts: hisi: add RoCE nodes for the hip07 SoC arm64: dts: hisi: add network related nodes for the hip07 SoC arm64: dts: hisi: add mbigen nodes for the hip07 SoC arm64: dts: rockchip: fix the memory size of PX5 Evaluation board arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board ...
2017-04-04ARM64: dts: meson-gx: Add support for HDMI outputNeil Armstrong1-0/+12
Add HDMI output and connector nodes. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-28ARM64: dts: meson-gxbb: add spdif output pinsjbrunet1-0/+21
Add EE and AO domains pins for the spdif output to the gxbb device tree. Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-28ARM64: dts: meson-gxbb: add i2s output pinsjbrunet1-0/+63
Add EE and AO domains pins for the i2s output clocks and data to the gxbb device tree. Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-28ARM64: dts: meson-gxbb: Add gpio-ranges propertiesNeil Armstrong1-0/+2
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-28ARM64: dts: meson-gx: Add Mali nodes for GXBB and GXLNeil Armstrong1-0/+37
The same Mali-450 MP3 GPU is present in the GXBB and GXL SoCs. The node is simply added in the meson-gxbb.dtsi file. For GXL, since a lot is shared with the GXM that has a Mali-T820 IP, this patch adds a new meson-gxl-mali.dtsi and is included in the SoC specific dtsi files. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> [khilman: s/MALI/Mali in changelog] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-23ARM64: dts: meson-gx: Finally move common nodes to GX dtsiNeil Armstrong1-35/+8
Since we know the GXBB and GXL/GXM share more hardware, we can safely move the remaining peripheral nodes present in the GXBB dtsi to the common GX dtsi. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-03-16ARM64: dts: meson-gx: add clock CLKID_RNG0 to hwrng nodeHeiner Kallweit1-0/+5
Add clock CLKID_RNG0 to HW randon number generator node. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-01-30ARM64: dts: meson: meson-gx: add the SAR ADCMartin Blumenstingl1-0/+10
Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a 10-bit ADC while GXL and GXM provide a 12-bit ADC. Some boards use resistor ladder buttons connected through one of the ADC channels. On newer devices (GXL and GXM) some boards use pull-ups/downs to change the resistance (and thus the ADC value) on one of the ADC channels to indicate the board revision. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-18ARM64: dts: meson-gx: Add HDMI HPD/DDC pinctrl nodesNeil Armstrong1-0/+14
Add pinctrl nodes for HDMI HPD and DDC pins modes for Amlogic Meson GXL and GXBB SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-18ARM64: dts: meson-gx: add the serial CTS and RTS pin groupsMartin Blumenstingl1-0/+40
This adds pinctrl group nodes for the CTS and RTS pins of each serial controller. This makes it possible to enable the CTS and RTS pins which are controlled by the serial controller hardware (through the meson_uart driver). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-18ARM64: dts: meson-gx: add the missing uart_AO_BMartin Blumenstingl1-0/+7
This adds the missing node for the uart_AO_B port to the meson-gx.dtsi (as this is supported by GXBB, GXL and GXM) along with the required pinctrl pins. This is required as some boards are using it (the boards from the Khadas VIM series for example have it exposed on the pin headers). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-10ARM64: dts: meson-gx: move the SCPI and SRAM nodes to meson-gxMartin Blumenstingl1-57/+0
SCPI and SRAM are identical on GXBB and GXL. Moving the corresponding nodes to meson-gx adds support for the thermal sensor on GXL based devices. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> [khilman: add scpi_clocks label] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
2017-01-03ARM64: dts: meson-gx: Add Graphic Controller nodesNeil Armstrong1-0/+4
Add Video Processing Unit and CVBS Output nodes, and enable CVBS on selected boards. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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