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path: root/drivers/gpu/drm/i915/gt/intel_gpu_commands.h (follow)
AgeCommit message (Expand)AuthorFilesLines
2021-10-04drm/i915/pxp: Implement arb session teardownHuang, Sean Z1-3/+19
2021-06-17drm/i915/gt: Pipelined page migrationChris Wilson1-0/+2
2021-05-19gpu: drm: replace occurrences of invalid characterMauro Carvalho Chehab1-1/+1
2021-03-24drm/i915/gt: SPDX cleanupChris Wilson1-2/+1
2020-05-07drm/i915/gen12: Fix HDC pipeline flushMika Kuoppala1-1/+1
2020-05-07Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"Mika Kuoppala1-1/+0
2020-04-25drm/i915: Add per ctx batchbuffer wa for timestampMika Kuoppala1-1/+2
2020-03-06drm/i915/gen7: Clear all EU/L3 residual contextsPrathap Kumar Valsan1-3/+14
2019-12-12drm/i915/gem: Prepare gen7 cmdparser for async executionChris Wilson1-0/+8
2019-12-11drm/i915: Remove redundant parameters from intel_engine_cmd_parserChris Wilson1-0/+21
2019-10-15drm/i915/tgl: Add HDC Pipeline FlushMika Kuoppala1-0/+1
2019-10-15drm/i915/tgl: Include ro parts of l3 to invalidateMika Kuoppala1-0/+1
2019-10-12drm/i915/perf: implement active wait for noa configurationsLionel Landwerlin1-1/+3
2019-10-12drm/i915/perf: allow for CS OA configs to be created lazilyLionel Landwerlin1-0/+1
2019-09-26drm/i915: Add definitions for MI_MATH commandMichał Winiarski1-0/+23
2019-09-26drm/i915: Adjust length of MI_LOAD_REGISTER_REGMichał Winiarski1-1/+1
2019-09-17drm/i915/tgl: Extend MI_SEMAPHORE_WAITChris Wilson1-0/+3
2019-09-06drm/i915: Use engine relative LRIs on context setupMika Kuoppala1-0/+2
2019-08-15drm/i915/icl: Add command cache invalidateMika Kuoppala1-0/+1
2019-08-15drm/i915/icl: Implement gen11 flush including tile cacheMika Kuoppala1-0/+1
2019-08-10drm/i915/blt: support copying objectsMatthew Auld1-4/+5
2019-07-11drm/i915/selftests: Ensure we don't clamp a random offset to 32bChris Wilson1-0/+7
2019-05-30drm/i915: add in-kernel blitter clientMatthew Auld1-0/+1
2019-04-24drm/i915: Move GraphicsTechnology files under gt/Chris Wilson1-0/+278
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