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* fpga: ci: Add testbench pipelineWade Fife2021-07-012-0/+106
* fpga: x400: Fix x4xx_qsfp_wrapper testbenchWade Fife2021-06-221-0/+3
* fpga: sim: Check for empty packet in clear_unused_bytesWade Fife2021-06-171-0/+4
* x400: sim: Move testbenches to sim folderWade Fife2021-06-1713-0/+0
* fpga: Update testbenches to work in ModelSimWade Fife2021-06-1711-136/+303
* fpga: x400: Add makefiles for RF testbenchesWade Fife2021-06-177-3/+212
* fpga: tools: Detect assertions in ModelSim simulationWade Fife2021-06-171-2/+22
* fpga: tools: Put SIM_SRCS at end of compile orderWade Fife2021-06-171-1/+1
* fpga: tools: Support new FPGA types in viv_simulator.makWade Fife2021-06-171-2/+2
* fpga: tools: Fix python2 reference in viv_ip_builder.makWade Fife2021-06-171-1/+1
* fpga: tools: Add modelsim.excludesWade Fife2021-06-171-0/+18
* fpga: tools: Add modelsim.ini to ModelSim callsWade Fife2021-06-174-7/+38
* fpga: tools: Add features to run_testbenches.pyWade Fife2021-06-171-6/+19
* fpga: tools: Add ip target to simulation makefilesWade Fife2021-06-172-2/+6
* fpga: tools: Add X410 support for image packagingHumberto Jimenez2021-06-101-0/+24
* fpga: ci: Add build definitions for FPGA CIWade Fife2021-06-107-0/+483
* fpga: x400: zbx: Add support for ZBX CPLDJavier Valenzuela2021-06-1037-0/+17727
* fpga: x400: cpld: Add support for X410 motherboard CPLDMax Köhler2021-06-1042-0/+8377
* fpga: x400: Add support for X410 motherboard FPGAWade Fife2021-06-10207-1/+299667
* fpga: sim: Add slave_idle() to PkgAxiStreamBfm.svWade Fife2021-06-101-0/+4
* fpga: lib: Update register comments in eth_regs.vhWade Fife2021-06-101-1/+5
* fpga: Update rfnoc_image_core for all targetsWade Fife2021-06-1018-5780/+6492
* fpga: Update recommended HDL header guidelineWade Fife2021-06-101-0/+3
* fpga: tools: Fix part selection in setupenvSam O'Brien2021-06-101-4/+12
* fpga: Change RFNoC YAML version numbers to stringsWade Fife2021-06-0810-20/+20
* fpga: lib: Add modports to SV AXI-Stream blocksWade Fife2021-06-034-8/+8
* fpga: lib: Add time_increment port to timekeeperWade Fife2021-06-031-17/+43
* fpga: lib: Pipeline ctrlport_timerWade Fife2021-06-031-24/+81
* fpga: lib: Add clock domain comments to interfacesWade Fife2021-06-037-13/+28
* fpga: lib: Add 2 to 1 gearbox moduleWade Fife2021-06-035-0/+517
* fpga: lib: Add PHASE parameter to sim_clk_genWade Fife2021-06-031-1/+3
* fpga: lib: Add AXI4 (full) interfaceAndrew Moch2021-06-034-0/+619
* fpga: lib: add pause support to ethernet xportAndrew Moch2021-06-036-7/+112
* fpga: lib: Add eth_ipv4_internalWade Fife2021-06-032-0/+442
* fpga: lib: Add zynquplus family to axi_bitqHumberto Jimenez2021-06-031-12/+13
* fpga: tools: Add ability to run commands before routeWade Fife2021-06-031-5/+11
* fpga: tools: Add ability to patch IP during generationWade Fife2021-06-032-0/+87
* fpga: tools: Add support for RFSoCHumberto Jimenez2021-06-032-9/+9
* fpga: lib: Minor cleanup of axi_lite.vhLars Amsel2021-06-031-2/+23
* fpga: rfnoc: Add ability to disable output flow controlWade Fife2021-04-142-7/+22
* fpga: lib: Add rx_front_end_gen3 testbenchWade Fife2021-04-092-0/+247
* fpga: lib: Update round_sd to eliminate X from simulationWade Fife2021-04-091-14/+45
* fpga: lib: Fix simulation of axi_fir_filterWade Fife2021-04-091-1/+1
* TwinRX: Remove frontend filtermichael-west2021-04-081-59/+8
* fpga: docs: Improve documentation of rx_frontend_gen3Martin Braun2021-04-071-1/+73
* fpga: lib: Fix DDS_SIN_COS_LUT outputs in makefilePaul Butler2021-03-311-1/+1
* fpga: dsp: Fix formatting of rx_dcoffset and add docsMartin Braun2021-03-091-38/+110
* fpga: Remove Python2 support from build systemMartin Braun2021-01-0417-119/+121
* fpga: e320: Improve timing on LVDS interfaceWade Fife2020-12-114-358/+541
* fpga: lib: add glitch free mux moduleMax Köhler2020-12-032-0/+30
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