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2024-07-01arm64: dts: qcom: move common parts for sa8775p-ride variants into a .dtsiBartosz Golaszewski1-813/+21
In order to support multiple revisions of the sa8775p-ride board, create a .dtsi containing the common parts and split out the ethernet bits into the actual board file as they will change in revision 3. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20240627114212.25400-3-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-12-07arm64: dts: qcom: sa8775p-ride: enable pmm8654au_0_pon_resinShazad Hussain1-0/+5
The volume down key is controlled by PMIC via the PON hardware on sa8775p platform, so enable the same for sa8775p-ride. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Link: https://lore.kernel.org/r/20231107120503.28917-1-quic_shazhuss@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19arm64: dts: qcom: sa8775p-ride: Describe sgmii_phy1 irqAndrew Halaney1-0/+1
There's an irq hooked up, so let's describe it. Prior to commit 9757300d2750 ("pinctrl: qcom: Add intr_target_width field to support increased number of interrupt targets") one would not see the IRQ fire, despite some (invasive) debugging showing that the GPIO was in fact asserted, resulting in the interface staying down. Now that the IRQ is properly routed we can describe it. Signed-off-by: Andrew Halaney <ahalaney@redhat.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230817213815.638189-3-ahalaney@redhat.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-09-19arm64: dts: qcom: sa8775p-ride: Describe sgmii_phy0 irqAndrew Halaney1-0/+1
There's an irq hooked up, so let's describe it. Prior to commit 9757300d2750 ("pinctrl: qcom: Add intr_target_width field to support increased number of interrupt targets") one would not see the IRQ fire, despite some (invasive) debugging showing that the GPIO was in fact asserted, resulting in the interface staying down. Now that the IRQ is properly routed we can describe it. Signed-off-by: Andrew Halaney <ahalaney@redhat.com> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230817213815.638189-2-ahalaney@redhat.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-30Merge tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds1-2/+277
Pull ARM devicetree updates from Arnd Bergmann: "These are the devicetree updates for Arm and RISC-V based SoCs, mainly from Qualcomm, NXP/Freescale, Aspeed, TI, Rockchips, Samsung, ST and Starfive. Only a few new SoC got added: - TI AM62P5, a variant of the existing Sitara AM62x family - Intel Agilex5, an FPGFA platform that includes an Cortex-A76/A55 SoC. - Qualcomm ipq5018 is used in wireless access points - Qualcomm SM4450 (Snapdragon 4 Gen 2) is a new low-end mobile phone platform. In total, 29 machines get added, which is low because of the summer break. These cover SoCs from Aspeed, Broadcom, NXP, Samsung, ST, Allwinner, Amlogic, Intel, Qualcomm, Rockchip, TI and T-Head. Most of these are development and reference boards. Despite not adding a lot of new machines, there are over 700 patches in total, most of which are cleanups and minor fixes" * tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (735 commits) arm64: dts: use capital "OR" for multiple licenses in SPDX ARM: dts: use capital "OR" for multiple licenses in SPDX arm64: dts: qcom: sdm845-db845c: Mark cont splash memory region as reserved ARM: dts: qcom: apq8064: add support to gsbi4 uart riscv: dts: change TH1520 files to dual license riscv: dts: thead: add BeagleV Ahead board device tree dt-bindings: riscv: Add BeagleV Ahead board compatibles ARM: dts: stm32: add SCMI PMIC regulators on stm32mp135f-dk board ARM: dts: stm32: STM32MP13x SoC exposes SCMI regulators dt-bindings: rcc: stm32: add STM32MP13 SCMI regulators IDs ARM: dts: stm32: support display on stm32f746-disco board ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f746-disco ARM: dts: stm32: add pin map for LTDC on stm32f7 ARM: dts: stm32: add ltdc support on stm32f746 MCU arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sc8280xp: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sdm670: Add PDC riscv: dts: starfive: fix jh7110 qspi sort order ...
2023-08-11arm64: dts: qcom: sa8775p-ride: enable EMAC1Bartosz Golaszewski1-0/+71
Enable the second MAC on sa8775p-ride. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230810080909.6259-10-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-11arm64: dts: qcom: sa8775p-ride: add an alias for ethernet0Bartosz Golaszewski1-0/+1
Once we add a second ethernet node, the MDIO bus names will conflict unless we provide aliases. Add one for the existing ethernet node. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230810080909.6259-9-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-11arm64: dts: qcom: sa8775p-ride: sort aliases alphabeticallyBartosz Golaszewski1-2/+2
For improved readability order the aliases alphabetically for sa8775p-ride. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230810080909.6259-8-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-11arm64: dts: qcom: sa8775p-ride: add the second SGMII PHYBartosz Golaszewski1-0/+9
Add a second SGMII PHY that will be used by EMAC1 on sa8775p-ride. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230810080909.6259-7-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-11arm64: dts: qcom: sa8775p-ride: index the first SGMII PHYBartosz Golaszewski1-2/+2
We'll be adding a second SGMII PHY on the same MDIO bus, so let's index the first one for better readability. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230810080909.6259-6-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-11arm64: dts: qcom: sa8775p-ride: move the reset-gpios property of the PHYBartosz Golaszewski1-4/+4
Device-tree bindings for MDIO define per-PHY reset-gpios as well as a global reset-gpios property at the MDIO node level which controls all devices on the bus. The latter is most likely a workaround for the chicken-and-egg problem where we cannot read the ID of the PHY before bringing it out of reset but we cannot bring it out of reset until we've read its ID. I have proposed a comprehensive solution for this problem in 2020 but it never got upstream. We do however have workaround in place which allows us to hard-code the PHY id in the compatible property, thus skipping the ID scanning. Let's make the device-tree for sa8775p-ride slightly more correct by moving the reset-gpios property to the PHY node with its ID put into the PHY node's compatible. Link: https://lore.kernel.org/all/20200622093744.13685-1-brgl@bgdev.pl/ Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230810080909.6259-5-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-08-11arm64: dts: qcom: sa8775p-ride: enable the second SerDes PHYBartosz Golaszewski1-0/+5
Enable the second SerDes PHY on sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Andrew Halaney <ahalaney@redhat.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230810080909.6259-4-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-21arm64: dts: qcom: sa8775p-ride: enable pcie nodesMrinmay Sarkar1-0/+80
Enable pcie0, pcie1 nodes and their respective phy's. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Link: https://lore.kernel.org/r/1689960276-29266-5-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-13arm64: dts: qcom: sa8775p-ride: Update L4C parametersNaveen Kumar Goud Arepalli1-2/+2
L4c is the supply for UFS vccq, As per UFS spec range of vccq is 1.14V to 1.26V, There are stability issues when operating at marginal voltage. Hence configure the min and max vccq voltages to 1.2V. Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20230711105915.30581-1-quic_narepall@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-09arm64: dts: qcom: sa8775p-ride: enable ethernet0Bartosz Golaszewski1-0/+88
Enable the first 1Gb ethernet port on sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230622120142.218055-6-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-09arm64: dts: qcom: sa8775p-ride: add pin functions for ethernet0Bartosz Golaszewski1-0/+16
Add the MDC and MDIO pin functions for ethernet0 on sa8775p-ride. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230622120142.218055-5-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-07-09arm64: dts: qcom: sa8775p-ride: enable the SerDes PHYBartosz Golaszewski1-0/+5
Enable the internal PHY on sa8775p-ride. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> Link: https://lore.kernel.org/r/20230622120142.218055-4-brgl@bgdev.pl Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2023-05-26arm64: dts: qcom: sa8775p-ride: enable i2c11Shazad Hussain1-0/+15
This enables the i2c11 node on sa8775p-ride board for A2B controller and audio port expander. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230526133122.16443-6-quic_shazhuss@quicinc.com
2023-05-14arm64: dts: qcom: sa8775p-ride: enable USB nodesShazad Hussain1-0/+92
Enable usb0, usb1 and usb2 nodes and their respective phy's. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Adrien Thierry <athierry@redhat.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230428130824.23803-7-quic_shazhuss@quicinc.com
2023-05-14arm64: dts: qcom: sa8775p-ride: enable UFSBartosz Golaszewski1-0/+19
Enable the UFS and its PHY on sa8775p-ride. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230411130446.401440-6-brgl@bgdev.pl
2023-04-07arm64: dts: qcom: sa8775p-ride: add PMIC regulatorsBartosz Golaszewski1-0/+233
Add PMIC regulators for sa8775p-ride. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230406192811.460888-4-brgl@bgdev.pl
2023-04-04arm64: dts: qcom: sa8775p-ride: set gpio-line-names for PMIC GPIOsBartosz Golaszewski1-0/+51
Set line names for GPIO lines exposed by PMICs on sa8775p-ride. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230327125316.210812-16-brgl@bgdev.pl
2023-04-04arm64: dts: qcom: sa8775p: add support for the on-board PMICsBartosz Golaszewski1-0/+1
Add a new .dtsi file for sa8775p PMICs and add the four PMICs interfaced to the SoC via SPMI. Enable the PMICs for sa8775p-ride. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230327125316.210812-8-brgl@bgdev.pl
2023-03-21arm64: dts: qcom: sa8775p-ride: enable the BT UART portBartosz Golaszewski1-0/+33
Enable the high-speed UART port connected to the Bluetooth controller on the sa8775p-adp development board. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230309103752.173541-10-brgl@bgdev.pl
2023-03-21arm64: dts: qcom: sa8775p-ride: enable the GNSS UART portBartosz Golaszewski1-0/+33
Enable the high-speed UART port connected to the GNSS controller on the sa8775p-adp development board. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230309103752.173541-9-brgl@bgdev.pl
2023-03-21arm64: dts: qcom: sa8775p-ride: enable the SPI nodeBartosz Golaszewski1-0/+14
Enable the SPI interface exposed on the sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230309103752.173541-7-brgl@bgdev.pl
2023-03-21arm64: dts: qcom: sa8775p-ride: enable i2c18Bartosz Golaszewski1-0/+15
This enables the I2C interface on the sa8775p-ride development board. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230309103752.173541-5-brgl@bgdev.pl
2023-03-21arm64: dts: qcom: sa8775p-ride: enable QUPv3 #2Bartosz Golaszewski1-0/+4
Enable the second instance of the QUPv3 engine on the sa8775p-ride board. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230309103752.173541-3-brgl@bgdev.pl
2023-03-14arm64: dts: qcom: add initial support for qcom sa8775p-rideBartosz Golaszewski1-0/+47
This adds basic support for the Qualcomm sa8775p platform and the reference board: sa8775p-ride. The dt files describe the basics of the SoC and enable booting to shell. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230214092713.211054-3-brgl@bgdev.pl
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