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* spellingjsg2021-03-111-2/+2
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* Userland timecounter implementation for octeonvisa2020-07-182-1/+25
| | | | OK naddy@; no objections from kettenis@
* Synchronize each core's CP0 cycle counter using the IO clock counter.visa2020-07-111-1/+2
| | | | | | | | | | | This makes the cycle counter usable as timecounter on multiprocessor machines. Idea from Linux. Tested on CN5020, CN6120, CN7130 and CN7360. Looks reasonable to kettenis@
* do not need these versions of timetc.hderaadt2020-07-081-23/+0
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* Add support for timeconting in userland.pirofti2020-07-061-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | This diff exposes parts of clock_gettime(2) and gettimeofday(2) to userland via libc eliberating processes from the need for a context switch everytime they want to count the passage of time. If a timecounter clock can be exposed to userland than it needs to set its tc_user member to a non-zero value. Tested with one or multiple counters per architecture. The timing data is shared through a pointer found in the new ELF auxiliary vector AUX_openbsd_timekeep containing timehands information that is frequently updated by the kernel. Timing differences between the last kernel update and the current time are adjusted in userland by the tc_get_timecount() function inside the MD usertc.c file. This permits a much more responsive environment, quite visible in browsers, office programs and gaming (apparently one is are able to fly in Minecraft now). Tested by robert@, sthen@, naddy@, kmos@, phessler@, and many others! OK from at least kettenis@, cheloha@, naddy@, sthen@
* Remove obsolete <machine/stdarg.h> header. Nowadays the varargvisa2020-06-301-247/+0
| | | | | | | | functionality is provided by <sys/stdarg.h> using compiler builtins. Tested in a ports bulk build on amd64 by naddy@ OK naddy@ mpi@
* introduce "cpu_rnd_messybits" for use instead of nanotime in dev/rnd.c.dlg2020-05-311-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | rnd.c uses nanotime to get access to some bits that change quickly between events that it can mix into the entropy pool. it doesn't use nanotime to get a monotonically increasing set or ordered and accurate timestamps, it just wants something with bits that change. there's been discussions for years about letting rnd use a clock that's super fast to read, but not necessarily accurate, but it wasn't until recently that i figured out it wasn't interested in time at all, so things like keeping a fast clock coherent between cpu cores or correct according to ntp is unecessary. this means we can just let rnd read the cycle counters on cpus and things will be fine. cpus with cycle counters that vary in their speed and arent kept consistent between cores may even be desirable in this context. so this is the first step in converting rnd.c to reading cycle counter. it copies the nanotime backend to each arch, and they can replace it with something MD as a second step later on. djm@ suggested rnd_messybytes, but we landed on cpu_rnd_messybits. thanks to visa for his eyes. ok deraadt@ visa@ deraadt@ says he will help handle any MD fallout that occurs.
* Retire <machine/varargs.h>.visa2020-05-271-50/+0
| | | | | | Nothing uses the header anymore. OK deraadt@ mpi@
* Convert db_addr_t -> vaddr_t but leave the typedef for now.mpi2019-11-071-4/+4
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* Substitute boolean_t/TRUE/FALSE by int/1/0.mpi2019-11-071-2/+2
| | | | ok dlg@, jasper@
* Fix atomic_sub_long_nv() on mips64. The negation should usevisa2019-10-281-2/+2
| | | | 64-bit unsigned arithmetic.
* in non-MP, cpu_number() the #define should be 0UL; ok visaderaadt2019-09-021-2/+2
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* Fix a race in invalidation of remote TLB entries.visa2019-08-211-1/+2
| | | | | | | | | | | | | | If a CPU updates a pmap concurrently with the activation of that pmap on another CPU, invalidation of TLB entries might be incomplete. It is also possible that a CPU altogether stops updating its TLB. Prevent the race by synchronizing pmap activations and logic that determines where to send TLB invalidation IPIs. To avoid mutex wait without ability to process IPIs, the context switch code is adjusted to call pmap_activate() with interrupts enabled. In practice, interrupts up to IPL_SCHED are still disabled on context switch.
* Turn need_resched() and signotify() into proper functions on mips64.visa2019-05-051-12/+3
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* Guard against repeated inclusion of <mips64/pte.h>. This fixes drm buildvisa2019-04-261-1/+6
| | | | on loongson.
* Work around a limitation of clang integrated assembler on mips64.visa2019-04-191-1/+2
| | | | | | | | | The assembler does not handle undeclared local symbols properly and generates R_MIPS_CALL16 relocations where it should generate local GOT references. For now, get along with the problem by declaring local symbols where necessary. OK kettenis@ guenther@
* Use the debugger mutex for `ddb_mp_mutex'. This should prevent a racevisa2019-03-231-3/+1
| | | | | | | | | | that could leave `ddb_mp_mutex' locked if one CPU incremented `db_active' while another CPU was in the critical section. When the race hit, the debugger was unable to resume execution or switch between CPUs. Race analyzed by patrick@ OK mpi@ patrick@
* Include srp.h where struct cpu_info uses srp to avoid erroring out whenjsg2018-12-051-1/+2
| | | | | | | including cpu.h machine/intr.h etc without first including param.h when MULTIPROCESSOR is defined. ok visa@
* Add processor IDs for several OCTEON II and III SoCs.visa2018-12-041-1/+5
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* More "explicitely" -> "explicitly" in various comments.krw2018-10-221-2/+2
| | | | ok guenther@ tb@ deraadt@
* Unify and bump some of the NMBCLUSTERS defines. Some archs had it set toclaudio2018-09-141-2/+2
| | | | | | | | | 4MB which is far too low especially when the platform is able to run MP. New limits are, amd64 = 256M; arm64, mips64, sparc64 = 64M; alpha, arm, hppa, i386, powerpc = 32M; m88k, sh = 8M Still rather conservative numbers but much better than before. At least some hangs of arm64 build boxes was caused by this. OK kettenis@, visa@
* Add a driver for the OCTEON cryptographic unit. It providesvisa2018-04-091-1/+2
| | | | | | | | | | | | | | | | | | | a hardware-accelerated implementation of several encryption and authentication algorithms for ipsec(4): AES-CBC AES-CTR AES-GCM AES-GMAC HMAC-MD5 HMAC-SHA1 HMAC-SHA2-256 HMAC-SHA2-384 HMAC-SHA2-512 Please note that the driver is currently disabled. OK deraadt@
* #define _MAX_PAGE_SHIFT in MD _types.h as the maximum pagesize an archderaadt2018-03-051-1/+2
| | | | | | | | | | needs (looking at you sgi, but others required this before). This is for the circumstances we need pagesize known at compile time, not getpagesize() runtime. Use it for malloc storage sizes, for shm, and to set pthread stack default sizes. The stack sizes were a mess, and pushing them towards page-aligned is healthy move (which will also be needed by the coming stack register checker) ok guenther kettenis, discussion with stefan
* Declare ci_ipl volatile to prevent the compiler from optimizingvisa2018-02-241-2/+2
| | | | | | | | | | | | | | | | | | or reordering accesses to the variable. Assume that the assembler preserves the correct sequence of instructions, which allows the removal of the explicit noreorder/reorder toggles from the C code. With ci_ipl being volatile, drop mips_sync() calls that follow the accesses of the variable. The sync is redundant as a compiler barrier. In addition, the MIPS64 CPU designs should not need the sync for pipeline or write buffer control. According to miod@, the use of the instruction is a carryover from code targeting early MIPS designs that lack tight integration with the cache and write buffer. Discussed with and testing help from miod@. Tested on CN5020, CN6120, CN7130, CN7360, Loongson 2F and 3A1000, R4400, R8000, R10000 and R16000.
* Drop unused field `ci_ipiih'.visa2018-01-291-2/+1
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* Move common mutex implementations to a MI place.mpi2018-01-251-84/+2
| | | | | | Archs not yet converted can to the jump by defining __USE_MI_MUTEX. ok visa@
* Unify <machine/mutex.h> a bit further.mpi2018-01-121-2/+2
| | | | | | `mtx_owner' becomes the first field of 'struct mutex' on i386/amd64/arm64. ok visa@
* Move SC_* defines into <machine/setjmp.h>, and rename them,visa2018-01-082-16/+7
| | | | | | so that <machine/signal.h> is not needed in setjmp.S. Suggested by kettenis@ long ago, OK deraadt@
* Unify <machine/mutex.h> a bit further.mpi2018-01-041-2/+2
| | | | | | | Remove `mtx_lock' from i386, add volatile before `mtx_owner' where it was missing. Inputs from kettenis@, ok visa@
* Use MI mplock on mips64.visa2017-10-212-46/+16
| | | | OK mpi@
* Move mutex, condvar, and thread-specific data routes, pthread_once, andguenther2017-09-051-5/+1
| | | | | | | | pthread_exit from libpthread to libc, along with low-level bits to support them. Major bump to both libc and libpthread. Requested by libressl team. Ports testing by naddy@ ok kettenis@
* Let the kernel utilize the FPU if one is available, even when thevisa2017-09-021-1/+7
| | | | | | | | | | | FPUEMUL option is enabled. This benefits OCTEON III systems which can run floating-point operations natively. Feedback from and OK miod@; he also helped with testing. Tested on octeon without FPU (CN5020, CN6120) and with FPU (CN7130), as well as on sgi/IP27 (MP R16000), sgi/IP32 (R5000), and loongson (3A1000).
* Rely on the hardware to clear hazards on octeon.visa2017-08-271-1/+12
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* Use macros for Config1 bits.visa2017-08-261-1/+27
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* Make R_MIPS_* defines available via <machine/reloc.h>.visa2017-08-132-28/+48
| | | | OK guenther@
* Add a dummy (for now) <machine/reloc.h> for mips64 to fix build.visa2017-08-121-0/+10
| | | | OK guenther@
* Define MAXCPUS per mips64 port.visa2017-07-301-2/+1
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* remove CPU_LIDSUSPEND/machdep.lidsuspendnatano2017-07-121-3/+3
| | | | "fire away!" tedu
* kill RCSID macros; discussed with millertderaadt2017-06-291-5/+1
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* Fix TLB size computation on OCTEON II and III. The CPUs have utilizedvisa2017-06-112-2/+18
| | | | | | the whole TLB space even before this. However, TLB initialization on boot and TLB flush on ASID wraparound have been incomplete. These have caused crashes of processes.
* Move loongson/octeon/sgi unmap_startup() under arch/mips64.visa2017-06-081-1/+3
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* Add an idle cycle implementation for R4600/R5000/RM7000 CPUs and theirvisa2017-05-241-1/+4
| | | | | | | | derivatives. This lets the kernel utilize the CPUs' Standby Mode to reduce the power consumption of an idle system. Suggested by and input from miod@. He also tested this patch on an RM7000 O2.
* Replace __cpu_cas() with atomic_cas_ulong().visa2017-05-191-7/+1
| | | | OK kettenis@
* Make atomic.h ready to be included in userland.mpi2017-05-151-2/+2
| | | | | | - keep setbits/clearbits inside _KERNEL ok visa@
* Hook up HPET as a timecounter.visa2017-05-101-1/+2
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* Get TCB address using the RDHWR instruction instead of __get_tcb().visa2017-04-201-1/+20
| | | | | | | | | | | This gives fast access to the address on systems that implement the UserLocal register. TCB caching is still used when running in the single-threaded mode in order not to penalize old systems. The kernel counterpart of this change must be in place before using this diff! With guenther@
* Make TCB address available to userspace via the UserLocal register.visa2017-04-204-6/+57
| | | | | | | | | | This lets programs get the address without a system call on OCTEON II and later. Add UserLocal load emulation for systems that do not implement the RDHWR instruction or the UserLocal register. OK guenther@
* Hook up mutex(9) to witness(4).visa2017-04-201-3/+15
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* Provide mips64 with kernel-facing TCB_{GET,SET} macros that store itguenther2017-04-132-3/+6
| | | | | | | in struct mdproc. With that, all archs have those and the __HAVE_MD_TCB macro can be unifdef'ed as always defined. ok kettenis@ visa@ jsing@
* Use __ASSEMBLER__ instead of __LANGUAGE_ASSEMBLY.visa2017-04-101-4/+4
| | | | | | The latter is not defined by clang. OK guenther@, kettenis@
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