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* Make it clearer where message "spurious interrupt" comes from.visa2019-09-011-2/+3
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* Remember to detach the event counter when disestablishingvisa2019-03-171-1/+2
| | | | an interrupt handler.
* Replace a hand-rolled linked list with SLIST.visa2019-03-171-32/+37
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* Let each interrupt controller driver choose how to implementvisa2019-03-171-1/+17
| | | | | | | intr_barrier(9). With this change, the barrier should finally work properly with cnmac(4) interrupts that have been assigned to secondary cores.
* Include header <sys/evcount.h> where event counters are used, so thatvisa2019-03-161-1/+2
| | | | header <machine/intr.h> can eventually stop including it on octeon.
* Use a locally defined intrhand in octciu.c to ease future changes.visa2019-03-151-9/+23
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* Fix the balancing of work queue interrupts.visa2019-03-141-2/+2
| | | | | | | | | | | | | | | The value of `ncpusfound' no longer reflects the number of cores that will be utilized by the kernel; it can be larger if secondary cores have not been enabled by the firmware. This can lead to incorrect assignment of work queue interrupts, making certain cnmac(4) ports unable to receive packets. This is a regression introduced in r1.108 of octeon/machdep.c. Correct the problem by using `ncpus' for the balancing. All secondary cores have been attached and the value is final by the time work queue interrupt handlers are set up. Network issue reported by krw@
* Declare ci_ipl volatile to prevent the compiler from optimizingvisa2018-02-241-11/+1
| | | | | | | | | | | | | | | | | | or reordering accesses to the variable. Assume that the assembler preserves the correct sequence of instructions, which allows the removal of the explicit noreorder/reorder toggles from the C code. With ci_ipl being volatile, drop mips_sync() calls that follow the accesses of the variable. The sync is redundant as a compiler barrier. In addition, the MIPS64 CPU designs should not need the sync for pipeline or write buffer control. According to miod@, the use of the instruction is a carryover from code targeting early MIPS designs that lack tight integration with the cache and write buffer. Discussed with and testing help from miod@. Tested on CN5020, CN6120, CN7130, CN7360, Loongson 2F and 3A1000, R4400, R8000, R10000 and R16000.
* Always lock the kernel lock with non-MP-safe interrupt handlers.visa2018-01-231-2/+2
| | | | Suggested by kettenis@
* Fix a stupid typo.visa2017-11-031-2/+2
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* Assign each cnmac(4) port its own input work group, and assignvisa2017-11-021-4/+22
| | | | | the interrupt processing of each work group to one of the available CPUs. This enables some parallelism in the early stages of packet Rx.
* Add handling for the third interrupt summary vector,visa2017-07-131-8/+44
| | | | needed by upcoming work.
* Get cpuid from `ci' to avoid an extra function call.visa2017-07-131-2/+2
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* Reorganize separate configuration fields into per-CPU structsvisa2017-07-121-34/+43
| | | | | to compact the data indexing. This additionally improves the cache locality of the data.
* Fix function name in panic message.visa2017-07-071-2/+2
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* Use a consistent naming for fdt attach arguments.visa2017-06-191-7/+7
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* Split octeon interrupt code into a glue layer and a CIU driver.visa2017-06-181-0/+563
This makes possible to add drivers for other interrupt controllers on the platform. The glue layer has been derived from arm64/armv7.
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