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path: root/sys/arch/octeon/dev/octeon_iobus.c (follow)
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* Attach packet interfaces to octpip to use fdt.visa2019-09-151-28/+2
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* Add a driver for the PCIe controller found on OCTEON II and OCTEON III.visa2019-09-071-1/+10
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* Allow two GMX instances on CN70xx/CN71xx to enable all portsvisa2017-09-061-1/+2
| | | | on the E300 boards.
* rework octuctl and its children to attach via fdtjmatthew2017-07-251-3/+1
| | | | ok visa@
* iobus_h is unused, remove it.visa2017-07-151-12/+1
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* Split octeon interrupt code into a glue layer and a CIU driver.visa2017-06-181-3/+1
| | | | | | | This makes possible to add drivers for other interrupt controllers on the platform. The glue layer has been derived from arm64/armv7.
* Process fdt before iobus devices. Needed later when interrupt andvisa2017-04-241-10/+11
| | | | MDIO controller drivers are attached using fdt.
* No GMX on CN73xx.visa2017-04-151-1/+4
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* Add fdt_attach_args and simplebus for implementing fdt-capablevisa2016-12-081-2/+16
| | | | | | drivers on octeon. Adapted from armv7. ok kettenis@
* Add support for the second GMX interface on Octeon II. This enablesvisa2016-06-221-3/+28
| | | | | | | ports eth[0-3] on 8-port EdgeRouters. Currently, port eth0 maps to network interface cnmac4, eth1 to cnmac5 etc. ok dlg@, tested by martijn@
* add octuctl, a driver for the Octeon II usb controller interface, andjmatthew2016-03-181-1/+3
| | | | | | attachments for ehci and ohci. ok uebayasi@ jasper@ visa@ mpi@
* Add a new flash driver for Octeon that allows access to the internalpirofti2015-07-201-1/+2
| | | | | | | | | | | | | | | memory on (at least) D-Link DSR500 machines. This follows the CFI specification with code borrowed from zrouter (FreeBSD). The idea, once the current driver is thoroughly tested, would be to move it to MI land. The prerequisites to MI are width, shift and row detection and handling. In the long run I hope to be able to also add wdc support. For now write support is disabled. Okay miod@, deraadt@.
* rework how iobus(4) finds and attaches devices.jasper2015-07-191-32/+58
| | | | | | | | | this allows us to get rid of the static list of children devices, using only a lookup table for address hints where needed. as a bonus this removes the 'octcf0: [..] not configured' mesage on machines w/o octcf(4). tested by pirofti@ on DSR-500 and ERL by me ok miod@
* make a comment more safe, there's no CRIME there.jasper2015-07-161-2/+2
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* Do not attempt to configure octhci, superseded by dwc2miod2015-07-131-5/+3
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* Get dwc2 working on octeon.jmatthew2015-04-261-9/+1
| | | | | | | | | - transplant the clock setup code from octhci - add a bus space tag to deal with dwc2 using little endian addressing - bump up the rx fifo size, necessary for umass/sd to work tested on an edgerouter lite, which can almost boot by itself now ok uebayasi@ (various parts), miod@ (bus space bits)
* Direct config glue for octdwctwo(4).uebayasi2015-02-111-1/+4
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* implement atomic operations using ll/sc, and convert rw_cas and callers of thejmatthew2014-09-301-2/+2
| | | | | | | pre-existing atomics to match. tested on sgi (octane) and octeon (erl) ok miod@ dlg@
* Add work-in-progress octeon USB host controller support.pirofti2014-07-091-2/+4
| | | | | | Not enabled for now. It's easier for me to work on it in-tree. Discussed with and okay miod@
* various format string fixes and remove -Wno-format from octeonjasper2014-05-101-2/+2
| | | | feedback/ok miod@
* Add support for the hardware random number generator on the octeons.pirofti2013-10-241-3/+5
| | | | | | | | | Works on my DSR-500 and on the edge router as reported on the mailing lists. Finished sometime in August/September, needs more testing/polishing. Similar diff from William Orr on tech@. Prodded by deraadt@, okay jasper@.
* move octeonreg.h to a more generic location and add multiple inclusionjasper2013-06-021-2/+2
| | | | | | guards while here. ok uebayasi@
* Don't include <mips64/archtype.h> when you don't need it.miod2012-10-031-3/+1
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* Ethernet driver merged from IIJ's contribution code.syuu2011-06-161-3/+16
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* obio renamed iobus, moved interrupt handler code to dev/octeon_intr.csyuu2011-05-081-0/+264