wireguard-openbsd - WireGuard implementation for the OpenBSD kernel

	Commit message (Collapse)	Author	Age	Files	Lines
*	We need more memory barriers on powerpc.	kettenis	2020-10-29	1	-7/+13
\| \| \| \|	ok tobhe@
*	Improve I/O functions to match Linux:	kettenis	2020-10-26	1	-9/+100
\| \| \| \| \| \| \| \| \| \|	- Reverse byte order on big-endian architectures (except on sparc64) - Add memory barriers Note that sparc64 is special as we use a little-endian mapping for PCI bus space, so we shouldn't reverse the byte order there. ok jsg@
*	update drm to linux 5.7	jsg	2020-06-08	1	-0/+9
\| \| \| \| \| \| \| \| \| \|	adds kernel support for amdgpu: vega20, raven2, renoir, navi10, navi14 inteldrm: icelake, tigerlake Thanks to the OpenBSD Foundation for sponsoring this work, kettenis@ for helping, patrick@ for helping adapt rockchip drm and many developers for testing.
*	Update shared drm code, inteldrm(4) and radeondrm(4) from linux 4.4 to	jsg	2019-04-14	1	-0/+71
	linux 4.19.34. Adds support for more Intel hardware: Broxton/Apollo Lake (was is_preliminary in 4.4) Amber Lake (another Kaby Lake refresh) Gemini Lake Coffee Lake Whiskey Lake Cannon Lake (though no hardware with Intel graphics ever shipped) Ice Lake (alpha support, hardware not released) This does not add support for new radeon hardware on the AMD side as newer radeons have a different kernel driver (amdgpu). Thanks to the OpenBSD Foundation for sponsoring this work, kettenis@ for helping and a bunch of other developers for testing.